Relative Phase Offset Estimation and Correction

[SpongeBobaa]

I did phase correction according to the instructions on the wiki. But I got the following results.

It looks like my channel B is not working. Is this my X310 problem? How should I solve this problem?

[SpongeBobaa]

I have received the following display. Did the warning affect my results?

[INFO] [UHD] linux; GNU C++ version 7.5.0; Boost_106501; UHD_3.15.0.HEAD-0-gaea0e2de
[INFO] [X300] X300 initialization sequence...
[INFO] [X300] Maximum frame size: 1472 bytes.
[INFO] [X300] Radio 1x clock: 200 MHz
[INFO] [0/DmaFIFO_0] Initializing block control (NOC ID: 0xF1F0D00000000000)
[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1302 MB/s)
[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1317 MB/s)
[INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD100000000001)
[INFO] [0/Radio_1] Initializing block control (NOC ID: 0x12AD100000000001)
[INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0000000000000)
[INFO] [0/DDC_1] Initializing block control (NOC ID: 0xDDC0000000000000)
[INFO] [0/DUC_0] Initializing block control (NOC ID: 0xD0C0000000000000)
[INFO] [0/DUC_1] Initializing block control (NOC ID: 0xD0C0000000000000)
[WARNING] [X300] Cannot update master clock rate! X300 Series does not allow changing the clock rate during runtime.
[INFO] [MULTI_USRP] 1) catch time transition at pps edge
[INFO] [MULTI_USRP] 2) set times next pps (synchronously)
[WARNING] [MULTI_USRP] At least one channel is using an external LO.Using a manual DSP frequency policy is recommended to ensure the same frequency shift on all channels.

[michaelld]

OK so this is related to EttusResearch/uhd#675 ... yes? Let's go to email for this discussion ... but, yes that WARNING seems significant ... I meanyou have 2x TwinRX & if they are not properly sharing LO then that's going to cause issues!