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Commit 6a9665f

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Sonic0anacromaniac
andcommitted
Fixed softreset (#132)
Co-authored-by: an4cr0n <[email protected]>
1 parent ff2b333 commit 6a9665f

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2 files changed

+13
-16
lines changed

2 files changed

+13
-16
lines changed

src/DW1000Ng.cpp

+6-10
Original file line numberDiff line numberDiff line change
@@ -1415,21 +1415,17 @@ namespace DW1000Ng {
14151415
}
14161416

14171417
void softwareReset() {
1418-
/* Sets SYS_XTI_CLOCK and write PMSC to all zero */
1418+
/* Disable sequencing and go to state "INIT" - (a) Sets SYSCLKS to 01 */
14191419
_disableSequencing();
14201420
/* Clear AON and WakeUp configuration */
14211421
_writeToRegister(AON, AON_WCFG_SUB, 0x00, LEN_AON_WCFG);
14221422
_writeToRegister(AON, AON_CFG0_SUB, 0x00, LEN_AON_CFG0);
14231423
_writeToRegister(AON, AON_CTRL_SUB, 0x02, LEN_AON_CTRL);
1424-
/* Reset TX,RX and PMSC */
1425-
byte pmscctrl0[LEN_PMSC_CTRL0];
1426-
_readBytes(PMSC, PMSC_CTRL0_SUB, pmscctrl0, LEN_PMSC_CTRL0);
1427-
pmscctrl0[3] = 0x00;
1428-
_writeBytesToRegister(PMSC, PMSC_CTRL0_SUB, pmscctrl0, LEN_PMSC_CTRL0);
1429-
delay(5);
1430-
/* Reset to all one softwareReset. Clock remain to SYS_XTI_CLOCK */
1431-
pmscctrl0[3] = 0xF0;
1432-
_writeBytesToRegister(PMSC, PMSC_CTRL0_SUB, pmscctrl0, LEN_PMSC_CTRL0);
1424+
/* (b) Clear SOFTRESET to all zero’s */
1425+
_writeToRegister(PMSC, PMSC_SOFTRESET_SUB, 0x00, LEN_PMSC_SOFTRESET);
1426+
delay(1);
1427+
/* (c) Set SOFTRESET to all ones */
1428+
_writeToRegister(PMSC, PMSC_SOFTRESET_SUB, 0xF0, LEN_PMSC_SOFTRESET);
14331429
}
14341430

14351431
/* ###########################################################################

src/DW1000NgRegisters.hpp

+7-6
Original file line numberDiff line numberDiff line change
@@ -319,17 +319,18 @@ constexpr uint16_t LEN_AON_CFG1 = 2;
319319
// PMSC
320320
constexpr uint16_t PMSC = 0x36;
321321
constexpr uint16_t PMSC_CTRL0_SUB = 0x00;
322+
constexpr uint16_t GPDCE_BIT = 18;
323+
constexpr uint16_t KHZCLKEN_BIT = 23;
324+
constexpr uint16_t PMSC_SOFTRESET_SUB = 0x03;
322325
constexpr uint16_t PMSC_CTRL1_SUB = 0x04;
326+
constexpr uint16_t ATXSLP_BIT = 11;
327+
constexpr uint16_t ARXSLP_BIT = 12;
323328
constexpr uint16_t PMSC_LEDC_SUB = 0x28;
329+
constexpr uint16_t BLNKEN = 8;
324330
constexpr uint16_t LEN_PMSC_CTRL0 = 4;
331+
constexpr uint16_t LEN_PMSC_SOFTRESET = 1;
325332
constexpr uint16_t LEN_PMSC_CTRL1 = 4;
326333
constexpr uint16_t LEN_PMSC_LEDC = 4;
327-
constexpr uint16_t GPDCE_BIT = 18;
328-
constexpr uint16_t KHZCLKEN_BIT = 23;
329-
constexpr uint16_t BLNKEN = 8;
330-
331-
constexpr uint16_t ATXSLP_BIT = 11;
332-
constexpr uint16_t ARXSLP_BIT = 12;
333334

334335
// TX_ANTD Antenna delays
335336
constexpr uint16_t TX_ANTD = 0x18;

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