- Circuit: 12-bit signed adders (no overflow)
- Selection criteria: pareto optimal sub-set wrt. pwr and ep parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add12se_5BQ | 0.0098 | 0.20 | 4.69 | 0.12 | 3.0 | [Verilog] [C] |
| add12se_54K | 0.0049 | 0.024 | 25.00 | 0.088 | 0.2 | [Verilog] [C] |
| add12se_58Y | 0.012 | 0.024 | 50.00 | 0.21 | 0.5 | [Verilog] [C] |
| add12se_59U | 0.02 | 0.049 | 62.50 | 0.28 | 1.0 | [Verilog] [C] |
| add12se_5AN | 0.034 | 0.098 | 78.12 | 0.53 | 3.0 | [Verilog] [C] |
| add12se_4ZY | 0.066 | 0.22 | 88.96 | 1.07 | 11 | [Verilog] [C] |
| add12se_5CX | 0.81 | 2.10 | 99.22 | 12.63 | 1513 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020