- Circuit: 12-bit unsigned adders
- Selection criteria: pareto optimal sub-set wrt. pwr and mae parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add12u_19A | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [VerilogPDK45] [C] |
| add12u_20A | 0.0061 | 0.012 | 50.00 | 0.017 | 0.5 | [Verilog] [C] |
| add12u_13K | 0.018 | 0.049 | 81.25 | 0.051 | 3.5 | [Verilog] [VerilogPDK45] [C] |
| add12u_1QE | 0.049 | 0.098 | 96.88 | 0.14 | 21 | [Verilog] [VerilogPDK45] [C] |
| add12u_0XE | 0.13 | 0.44 | 97.22 | 0.37 | 180 | [Verilog] [C] |
| add12u_1SA | 0.39 | 0.78 | 99.95 | 1.08 | 1242 | [Verilog] [VerilogPDK45] [C] |
| add12u_4X2 | 0.98 | 3.78 | 99.57 | 2.64 | 10471 | [Verilog] [C] |
| add12u_04U | 3.20 | 7.71 | 99.91 | 8.54 | 92047 | [Verilog] [C] |
| add12u_1KC | 6.25 | 12.50 | 100.00 | 16.24 | 325756 | [Verilog] [VerilogPDK45] [C] |
| add12u_2MB | 12.50 | 25.00 | 100.00 | 30.62 | 13015.54e2 | [Verilog] [C] |
- V. Mrazek, Z. Vasicek and R. Hrbacek, "Role of circuit representation in evolutionary design of energy-efficient approximate circuits" in IET Computers & Digital Techniques, vol. 12, no. 4, pp. 139-149, 7 2018. doi: 10.1049/iet-cdt.2017.0188
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020