- Circuit: 12-bit unsigned adders
- Selection criteria: pareto optimal sub-set wrt. pwr and mre parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add12u_19A | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [VerilogPDK45] [C] |
| add12u_20A | 0.0061 | 0.012 | 50.00 | 0.017 | 0.5 | [Verilog] [C] |
| add12u_08A | 0.026 | 0.061 | 87.50 | 0.07 | 6.0 | [Verilog] [C] |
| add12u_17B | 0.073 | 0.22 | 94.92 | 0.20 | 54 | [Verilog] [C] |
| add12u_013 | 0.21 | 0.82 | 97.84 | 0.58 | 474 | [Verilog] [C] |
| add12u_0HR | 0.50 | 1.67 | 99.28 | 1.39 | 2518 | [Verilog] [C] |
| add12u_2PX | 1.62 | 4.49 | 99.81 | 4.44 | 24176 | [Verilog] [C] |
| add12u_4M3 | 4.81 | 14.84 | 99.93 | 13.00 | 231551 | [Verilog] [C] |
| add12u_2MB | 12.50 | 25.00 | 100.00 | 30.62 | 13015.54e2 | [Verilog] [C] |
- V. Mrazek, Z. Vasicek and R. Hrbacek, "Role of circuit representation in evolutionary design of energy-efficient approximate circuits" in IET Computers & Digital Techniques, vol. 12, no. 4, pp. 139-149, 7 2018. doi: 10.1049/iet-cdt.2017.0188
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020