- Circuit: 16-bit unsigned adders
- Selection criteria: pareto optimal sub-set wrt. pwr and mse parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add16u_1E2 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| add16u_0NK | 0.002 | 0.0061 | 88.28 | 0.0054 | 10 | [Verilog] [C] |
| add16u_0Q7 | 0.0063 | 0.018 | 96.88 | 0.018 | 96 | [Verilog] [C] |
| add16u_0QC | 0.019 | 0.068 | 98.83 | 0.054 | 980 | [Verilog] [C] |
| add16u_0M0 | 0.057 | 0.19 | 99.61 | 0.16 | 8209 | [Verilog] [C] |
| add16u_0DL | 0.20 | 0.52 | 99.91 | 0.55 | 92039 | [Verilog] [C] |
| add16u_0M6 | 0.54 | 1.80 | 99.96 | 1.50 | 761357 | [Verilog] [C] |
| add16u_0QG | 1.63 | 4.63 | 99.99 | 4.52 | 62975.827e2 | [Verilog] [C] |
| add16u_0KC | 4.69 | 9.49 | 100.00 | 12.64 | 43382.861e3 | [Verilog] [C] |
| add16u_0MH | 9.90 | 34.18 | 100.00 | 22.35 | 25358.103e4 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020