- Circuit: 9-bit signed adders (no overflow)
- Selection criteria: pareto optimal sub-set wrt. pwr and mae parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add9se_07Y | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| add9se_09H | 0.14 | 0.39 | 62.45 | 1.64 | 1.0 | [Verilog] [C] |
| add9se_014 | 0.27 | 0.78 | 78.12 | 3.25 | 3.0 | [Verilog] [C] |
| add9se_0DX | 0.47 | 1.37 | 84.38 | 5.20 | 9.0 | [Verilog] [C] |
| add9se_0CU | 1.02 | 2.93 | 92.58 | 10.51 | 41 | [Verilog] [C] |
| add9se_09M | 1.82 | 6.05 | 96.88 | 15.90 | 128 | [Verilog] [C] |
| add9se_0A3 | 3.63 | 12.11 | 98.39 | 26.55 | 514 | [Verilog] [C] |
| add9se_080 | 7.32 | 24.61 | 99.21 | 44.90 | 2070 | [Verilog] [C] |
| add9se_0DV | 14.37 | 49.61 | 99.53 | 69.54 | 8574 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020