- Circuit: 9-bit signed adders (no overflow)
- Selection criteria: pareto optimal sub-set wrt. pwr and mre parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add9se_07Y | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| add9se_0CG | 0.098 | 0.20 | 50.00 | 1.27 | 0.5 | [Verilog] [C] |
| add9se_079 | 0.25 | 0.59 | 78.12 | 2.92 | 2.6 | [Verilog] [C] |
| add9se_0DX | 0.47 | 1.37 | 84.38 | 5.20 | 9.0 | [Verilog] [C] |
| add9se_0CU | 1.02 | 2.93 | 92.58 | 10.51 | 41 | [Verilog] [C] |
| add9se_0AD | 2.23 | 6.84 | 97.44 | 20.67 | 186 | [Verilog] [C] |
| add9se_0AY | 4.30 | 13.67 | 98.61 | 38.51 | 729 | [Verilog] [C] |
| add9se_0DV | 14.37 | 49.61 | 99.53 | 69.54 | 8574 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020