- Circuit: 9-bit signed adders (no overflow)
- Selection criteria: pareto optimal sub-set wrt. pwr and wce parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add9se_07Y | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| add9se_0CG | 0.098 | 0.20 | 50.00 | 1.27 | 0.5 | [Verilog] [C] |
| add9se_077 | 0.29 | 0.59 | 87.50 | 3.42 | 3.0 | [Verilog] [C] |
| add9se_0A8 | 0.43 | 0.98 | 87.50 | 5.17 | 7.5 | [Verilog] [C] |
| add9se_0C1 | 0.72 | 1.95 | 92.19 | 7.73 | 20 | [Verilog] [C] |
| add9se_07J | 1.46 | 3.12 | 98.83 | 16.69 | 68 | [Verilog] [C] |
| add9se_056 | 3.05 | 7.03 | 99.12 | 34.40 | 300 | [Verilog] [C] |
| add9se_07G | 6.13 | 12.50 | 99.92 | 71.05 | 1160 | [Verilog] [C] |
| add9se_0BB | 12.32 | 26.17 | 99.92 | 142.15 | 4705 | [Verilog] [C] |
| add9se_0DV | 14.37 | 49.61 | 99.53 | 69.54 | 8574 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020