- Circuit: 8x3-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and mre parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x3u_0KE | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x3u_1X9 | 0.012 | 0.39 | 3.12 | 0.12 | 2.0 | [Verilog] [C] |
| mul8x3u_1R5 | 0.012 | 0.049 | 25.00 | 0.32 | 0.25 | [Verilog] [C] |
| mul8x3u_1TK | 0.082 | 0.29 | 56.25 | 1.71 | 6.0 | [Verilog] [C] |
| mul8x3u_0SG | 0.20 | 0.63 | 76.17 | 3.72 | 30 | [Verilog] [C] |
| mul8x3u_1C9 | 0.51 | 1.95 | 83.98 | 8.21 | 200 | [Verilog] [C] |
| mul8x3u_0SF | 1.34 | 5.22 | 85.69 | 18.70 | 1309 | [Verilog] [C] |
| mul8x3u_1A4 | 4.36 | 13.62 | 86.91 | 43.25 | 13470 | [Verilog] [C] |
| mul8x3u_0QB | 21.79 | 87.16 | 87.16 | 100.00 | 380056 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020