- Circuit: 8x4-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and ep parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x4u_2UU | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x4u_35S | 0.0031 | 0.049 | 6.25 | 0.043 | 0.25 | [Verilog] [C] |
| mul8x4u_1AV | 4.32 | 56.25 | 17.24 | 9.73 | 336336 | [Verilog] [C] |
| mul8x4u_3AA | 0.018 | 0.049 | 37.50 | 0.50 | 1.5 | [Verilog] [C] |
| mul8x4u_2YS | 0.034 | 0.12 | 50.00 | 0.76 | 5.0 | [Verilog] [C] |
| mul8x4u_30G | 0.047 | 0.17 | 60.16 | 1.18 | 8.0 | [Verilog] [C] |
| mul8x4u_577 | 0.073 | 0.29 | 70.90 | 1.67 | 16 | [Verilog] [C] |
| mul8x4u_2JV | 0.17 | 0.63 | 81.93 | 3.59 | 84 | [Verilog] [C] |
| mul8x4u_555 | 23.35 | 93.38 | 93.38 | 100.00 | 16831.062e2 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020