- Circuit: 8x5-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and mae parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x5u_4E8 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x5u_00N | 0.0031 | 0.012 | 25.00 | 0.10 | 0.25 | [Verilog] [C] |
| mul8x5u_4B0 | 0.012 | 0.061 | 50.00 | 0.39 | 2.2 | [Verilog] [C] |
| mul8x5u_59A | 0.035 | 0.11 | 75.98 | 0.98 | 15 | [Verilog] [C] |
| mul8x5u_2UN | 0.10 | 0.40 | 85.21 | 2.40 | 110 | [Verilog] [C] |
| mul8x5u_3YD | 0.31 | 1.10 | 92.87 | 5.91 | 1058 | [Verilog] [C] |
| mul8x5u_2E0 | 0.95 | 4.00 | 95.95 | 15.33 | 9573 | [Verilog] [C] |
| mul8x5u_14C | 2.75 | 11.49 | 96.39 | 31.14 | 82463 | [Verilog] [C] |
| mul8x5u_0AP | 8.06 | 29.46 | 96.47 | 65.69 | 759638 | [Verilog] [C] |
| mul8x5u_541 | 24.12 | 96.50 | 96.50 | 100.00 | 70690.462e2 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020