- Circuit: 8x5-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and wce parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x5u_4E8 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x5u_5R9 | 0.0092 | 0.024 | 50.00 | 0.28 | 1.2 | [Verilog] [C] |
| mul8x5u_44H | 0.027 | 0.073 | 70.31 | 0.79 | 9.2 | [Verilog] [C] |
| mul8x5u_37F | 0.059 | 0.17 | 81.47 | 1.69 | 39 | [Verilog] [C] |
| mul8x5u_4CX | 0.18 | 0.62 | 90.62 | 3.83 | 356 | [Verilog] [C] |
| mul8x5u_613 | 0.47 | 1.66 | 94.41 | 8.50 | 2287 | [Verilog] [C] |
| mul8x5u_13K | 1.05 | 3.91 | 95.95 | 20.33 | 11334 | [Verilog] [C] |
| mul8x5u_2ML | 3.85 | 12.89 | 96.31 | 54.36 | 154522 | [Verilog] [C] |
| mul8x5u_280 | 10.42 | 34.07 | 96.48 | 66.45 | 12108.165e2 | [Verilog] [C] |
| mul8x5u_541 | 24.12 | 96.50 | 96.50 | 100.00 | 70690.462e2 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020