- Circuit: 8x7-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and mae parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x7u_0V5 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x7u_2SG | 0.00057 | 0.0031 | 18.75 | 0.028 | 0.19 | [Verilog] [C] |
| mul8x7u_3UT | 0.0033 | 0.012 | 53.12 | 0.13 | 2.8 | [Verilog] [C] |
| mul8x7u_4NF | 0.01 | 0.037 | 76.98 | 0.35 | 19 | [Verilog] [C] |
| mul8x7u_3EJ | 0.049 | 0.19 | 95.65 | 1.43 | 416 | [Verilog] [C] |
| mul8x7u_60Y | 0.13 | 0.54 | 96.12 | 3.19 | 2949 | [Verilog] [C] |
| mul8x7u_44V | 0.56 | 2.39 | 98.57 | 10.75 | 51673 | [Verilog] [C] |
| mul8x7u_2D5 | 1.97 | 7.96 | 98.73 | 25.98 | 638557 | [Verilog] [C] |
| mul8x7u_048 | 6.79 | 25.20 | 98.82 | 63.75 | 79116.74e2 | [Verilog] [C] |
| mul8x7u_4MC | 24.71 | 98.83 | 98.83 | 100.00 | 11722.021e4 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020