- Circuit: 8-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and ep parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8u_1JFF | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [VerilogPDK45] [C] |
| mul8u_1446 | 0.018 | 0.29 | 9.38 | 0.13 | 1792 | [Verilog] [C] |
| mul8u_JQQ | 1.12 | 15.53 | 19.82 | 2.64 | 55767.68e2 | [Verilog] [C] |
| mul8u_GS2 | 0.057 | 1.14 | 29.93 | 0.51 | 12684 | [Verilog] [C] |
| mul8u_7C1 | 0.13 | 2.38 | 39.93 | 1.04 | 52863 | [Verilog] [C] |
| mul8u_RCG | 0.43 | 4.48 | 49.91 | 2.61 | 386332 | [Verilog] [C] |
| mul8u_1CMB | 0.65 | 6.23 | 65.97 | 4.05 | 645336 | [Verilog] [C] |
| mul8u_L40 | 1.54 | 13.92 | 74.91 | 7.46 | 36892.825e2 | [Verilog] [C] |
| mul8u_YX7 | 4.84 | 49.22 | 88.71 | 15.66 | 33602.746e3 | [Verilog] [C] |
| mul8u_E9R | 24.81 | 99.22 | 99.22 | 100.00 | 47164.981e4 | [Verilog] [C] |
- V. Mrazek, R. Hrbacek, Z. Vasicek and L. Sekanina, "EvoApprox8b: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods". Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, Lausanne, 2017, pp. 258-261. doi: 10.23919/DATE.2017.7926993