- Circuit: 8-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and mre parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8u_1JFF | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [VerilogPDK45] [C] |
| mul8u_125K | 0.00095 | 0.0092 | 17.19 | 0.023 | 2.5 | [Verilog] [C] |
| mul8u_14VP | 0.0076 | 0.064 | 39.26 | 0.14 | 87 | [Verilog] [C] |
| mul8u_ZFB | 0.059 | 0.45 | 69.26 | 0.80 | 3147 | [Verilog] [C] |
| mul8u_12N4 | 0.43 | 2.15 | 87.31 | 4.20 | 139814 | [Verilog] [C] |
| mul8u_QKX | 5.09 | 49.23 | 97.47 | 21.95 | 34405.106e3 | [Verilog] [C] |
| mul8u_E9R | 24.81 | 99.22 | 99.22 | 100.00 | 47164.981e4 | [Verilog] [C] |
- V. Mrazek, R. Hrbacek, Z. Vasicek and L. Sekanina, "EvoApprox8b: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods". Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, Lausanne, 2017, pp. 258-261. doi: 10.23919/DATE.2017.7926993