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# Reading C:/intelFPGA_lite/17.0/modelsim_ase/tcl/vsim/pref.tcl
do runlab.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 08:53:22 on May 19,2025
# vlog -reportprogress 300 ./timescale.v
# End time: 08:53:22 on May 19,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 08:53:22 on May 19,2025
# vlog -reportprogress 300 ./i2c_master_defines.v
# End time: 08:53:22 on May 19,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 08:53:22 on May 19,2025
# vlog -reportprogress 300 ./i2c_master_bit_ctrl.v
# -- Compiling module i2c_master_bit_ctrl
#
# Top level modules:
# i2c_master_bit_ctrl
# End time: 08:53:23 on May 19,2025, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 08:53:23 on May 19,2025
# vlog -reportprogress 300 ./i2c_master_byte_ctrl.v
# -- Compiling module i2c_master_byte_ctrl
#
# Top level modules:
# i2c_master_byte_ctrl
# End time: 08:53:23 on May 19,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 08:53:23 on May 19,2025
# vlog -reportprogress 300 ./i2c_master_top.v
# -- Compiling module i2c_master_top
#
# Top level modules:
# i2c_master_top
# End time: 08:53:23 on May 19,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 08:53:23 on May 19,2025
# vlog -reportprogress 300 ./i2c_master_single_byte.v
# -- Compiling module i2c_master_single_byte
#
# Top level modules:
# i2c_master_single_byte
# End time: 08:53:23 on May 19,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 08:53:23 on May 19,2025
# vlog -reportprogress 300 ./i2c_master_single_byte_tb.v
# -- Compiling module i2c_master_single_byte_tb
#
# Top level modules:
# i2c_master_single_byte_tb
# End time: 08:53:23 on May 19,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 08:53:23 on May 19,2025
# vlog -reportprogress 300 ./i2c_master_top_tb.v
# -- Compiling module i2c_master_top_tb
#
# Top level modules:
# i2c_master_top_tb
# End time: 08:53:23 on May 19,2025, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -voptargs=""+acc"" -t 1ps -lib work i2c_master_single_byte_tb
# Start time: 08:53:23 on May 19,2025
# Loading work.i2c_master_single_byte_tb
# Loading work.i2c_master_single_byte
# Loading work.i2c_master_byte_ctrl
# Loading work.i2c_master_bit_ctrl
# End time: 08:53:34 on May 19,2025, Elapsed time: 0:00:11
# Errors: 0, Warnings: 0
# vsim -voptargs=""+acc"" -t 1ps -lib work i2c_master_top_tb
# Start time: 08:53:34 on May 19,2025
# Loading work.i2c_master_top_tb
# Loading work.i2c_master_top
# Loading work.i2c_master_byte_ctrl
# Loading work.i2c_master_bit_ctrl
# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
# File in use by: Max Lan Hostname: DESKTOP-MG7U4AC ProcessID: 47900
# Attempting to use alternate WLF file "./wlft05xddw".
# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
# Using alternate file: ./wlft05xddw
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body.tree
# Starting I2C Master Top Testbench
# 8516000: START condition detected
# 95547000: Address + R/W: 0xa2 (Addr: 0x51, R/W: 0)
# 106547000: Address ACK: 1
# 111703000: Status after address: RxACK=1, TIP=0
# 111703000: ERROR: Slave did not acknowledge address
# 205547000: Slave received data: 0xac
# 221547000: STOP condition detected
# 221703000: Status after data: RxACK=1, TIP=0
# 221703000: ERROR: Slave did not acknowledge data
#
# 321797000: Testbench Complete
# ** Note: $finish : ./i2c_master_top_tb.v(390)
# Time: 321796875 ps Iteration: 0 Instance: /i2c_master_top_tb
# 1
# Break in Module i2c_master_top_tb at ./i2c_master_top_tb.v line 390
# End time: 11:41:53 on May 19,2025, Elapsed time: 2:48:19
# Errors: 0, Warnings: 2