Merge pull request #117 from zapta/main

Added an example for the Brisbane 9K board.

Author: zapta

examples/brs-100-gw1nr9/blinky/apio.ini

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+; Apio project configuration file.
+; See https://fpgawars.github.io/apio/project-file for details.
+
+[env:default]
+board = brs-100-gw1nr9 
+top-module = blinky
+
+default-testbench = blinky_tb.v
+

examples/brs-100-gw1nr9/blinky/blinky.v

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+module blinky #(
+    // Num of clock cycle per led transition.
+    parameter integer DIV = (27000000 / 6)
+) (
+    input            sys_clk,
+    output reg [5:0] leds      // Active low
+);
+
+  // ---- Reset generator.
+
+  reg [3:0] reset_counter = 0;
+  reg sys_reset = 1;
+
+  always @(posedge sys_clk) begin
+    if (reset_counter < 3) begin
+      sys_reset <= 1;
+      reset_counter <= reset_counter + 1;
+    end else begin
+      sys_reset <= 0;
+    end
+  end
+
+  // ---- Blinker
+
+  reg [31:0] blink_counter;
+
+  always @(posedge sys_clk) begin
+    if (sys_reset) begin
+      // Reset
+      blink_counter <= 0;
+      leds <= 6'b111110;
+    end else if (blink_counter < (DIV - 1)) begin
+      // Delay
+      blink_counter <= blink_counter + 1;
+    end else begin
+      // Transition
+      blink_counter <= 0;
+      leds = {leds[4:0], leds[5]};
+    end
+  end
+
+endmodule

examples/brs-100-gw1nr9/blinky/blinky_tb.gtkw

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+[*]
+[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
+[*] Tue Feb 24 05:21:33 2026
+[*]
+[dumpfile] "/Users/user/work-brisbane/_build/default/blinky_tb.vcd"
+[dumpfile_mtime] "Tue Feb 24 05:19:52 2026"
+[dumpfile_size] 4425
+[savefile] "/Users/user/work-brisbane/blinky_tb.gtkw"
+[timestart] 0
+[size] 1280 600
+[pos] -1 -1
+*-12.255525 1900 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] blinky_tb.
+[sst_width] 253
+[signals_width] 185
+[sst_expanded] 1
+[sst_vpaned_height] 158
+@200
+-Clock
+@420
+blinky_tb.clk_num
+@28
+blinky_tb.sys_clk
+@200
+-
+-Reset Generator
+@22
+blinky_tb.ticker.reset_counter[3:0]
+@28
+blinky_tb.ticker.sys_reset
+@200
+-
+-
+-LED Blinker
+@22
+blinky_tb.ticker.blink_counter[31:0]
+@200
+-
+@800022
+blinky_tb.leds[5:0]
+@28
+(0)blinky_tb.leds[5:0]
+(1)blinky_tb.leds[5:0]
+(2)blinky_tb.leds[5:0]
+(3)blinky_tb.leds[5:0]
+(4)blinky_tb.leds[5:0]
+(5)blinky_tb.leds[5:0]
+@1001200
+-group_end
+[pattern_trace] 1
+[pattern_trace] 0

examples/brs-100-gw1nr9/blinky/blinky_tb.v

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+// A testbench for testing the blinky module.
+
+`timescale 10 ns / 1 ns
+
+module blinky_tb ();
+
+  // Clock.
+  reg     sys_clk = 0;
+  integer clk_num = 0;
+
+  always begin
+    #10 sys_clk = ~sys_clk;
+    if (sys_clk) clk_num = clk_num + 1;
+  end
+
+  // Outputs.
+  wire [5:0] leds;
+
+  // Tested module. Transition the leds every 5 clocks.
+  blinky #(
+      .DIV(5)
+  ) ticker (
+      .sys_clk(sys_clk),
+      .leds(leds)
+  );
+
+  // Test main
+  initial begin
+    $dumpvars(0, blinky_tb);
+
+    // Wait 100 clocks.
+    repeat (100) @(posedge sys_clk);
+
+    // End of test
+    $display("End of simulation");
+    $finish;
+  end
+
+endmodule

examples/brs-100-gw1nr9/blinky/info

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+Blinking led

examples/brs-100-gw1nr9/blinky/pinout.cst

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+
+// On board 27Mhz oscilator.
+IO_LOC "sys_clk"   52;
+IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
+
+// LEDs
+IO_LOC  "leds[0]"  16;
+IO_LOC  "leds[1]"  15;
+IO_LOC  "leds[2]"  14;
+IO_LOC  "leds[3]"  13;
+IO_LOC  "leds[4]"  11;
+IO_LOC  "leds[5]"  10;
+
+IO_PORT "leds[0]"  IO_TYPE=LVCMOS33  PULL_MODE=UP  DRIVE=8;
+IO_PORT "leds[1]"  IO_TYPE=LVCMOS33  PULL_MODE=UP  DRIVE=8;
+IO_PORT "leds[2]"  IO_TYPE=LVCMOS33  PULL_MODE=UP  DRIVE=8;
+IO_PORT "leds[3]"  IO_TYPE=LVCMOS33  PULL_MODE=UP  DRIVE=8;
+IO_PORT "leds[4]"  IO_TYPE=LVCMOS33  PULL_MODE=UP  DRIVE=8;
+IO_PORT "leds[5]"  IO_TYPE=LVCMOS33  PULL_MODE=UP  DRIVE=8;