Merge pull request #95 from zapta/master

Added comments to the getting started example.

Author: zapta

examples/alhambra-ii/getting-started/apio.ini

@@ -1,9 +1,15 @@
 ; Apio project file.
+;
+; This file defines the Apio project configuration.
+; See https://fpgawars.github.io/apio/docs/project-file for available
+; options.
 
+; This project has a single Apio env (aka target) called 'default'.
 [env:default]
 
-; Board id.
+; Board id. This project uses the Alhambra-ii board.
 board = alhambra-ii
 
-; Top module name (in main.v)
+; The name of the top Verilog module to build. This
+; is the module 'Main' in main.v
 top-module = Main

examples/alhambra-ii/getting-started/main.v

@@ -1,3 +1,4 @@
+// This Verilog file define the Main module of this blinky example.
 
 module Main #(
     parameter integer N = 3_000_000

examples/alhambra-ii/getting-started/main_tb.v

@@ -1,3 +1,8 @@
+// A testbench for automatic testing of the module verilog Main.
+// To run the testbench in batch mode, use the Apio 'test' command.
+// To run the testbench with graphical view of the signals, run the 
+// Apio 'sim' (as in simulate) command.
+
 `timescale 1ns / 1ps
 
 module testbench;

examples/alhambra-ii/getting-started/pinout.pcf

@@ -1,6 +1,9 @@
+# This file defines the mapping of the FPGA pin number to 
+# signal names as used in main.v. We included here only the
+# signals that actually used by this example.
 
 set_io LED1 37  # output
 set_io LED2 38  # output
 
-set_io CLK 49  # input
+set_io CLK  49  # input