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[0.1.8]

Changed

  • The command apio sim doesn't define anymore the macro INTERACTIVE_SIM. To distinguish if a testbench is run by apio sim or apio test use the macro APIO_SIM which has the values 1 and 0 respectivly.

  • The values in the project file apio.ini can now contain pre-defined macros https://fpgawars.github.io/apio/docs/project-file/#value-macros .

  • Restructured the FPGAs definition file fpgas.jsonc. This requires users that custom FPGAs definition in their projects to adapt the format. see ~/.apio/packages/definitions.fpgas.jsonc for examples.

  • Fine-tuned the parameters of Gowin build (e.g. add an optional family arg for the Gowin 20k FPGA).

  • Minor tweaks and refactoring of the commands tree for clarity.

  • Added to the openFPGAloader programmer definition the options --force-terminal-mode and --verify. If you have in your project a custom boards.jsonc or programmers.jsonc file, you may need to adjust them accordingly.

[0.1.7]

Changed

  • Added right-click context menu commands for apio format, apio sim, apio lint, and apio test. The context menu works in the VS Code explorer and in the editor.

  • Added a menu command to test only the default testbench, similar to the behavior of the sim command which tests the default-testbench defined in apio.ini, or the existing testbench if the project has exactly one testbench.

  • The sim command now creates automatically a .gtkw default file to have GTKWave showing the testbench signals when it opens. This selection of signals and their display setting can then be changed in GTKWave and saved a a user created .gtkw file. See more details in the documentation of the sim command at https://fpgawars.github.io/apio/docs/cmd-apio-sim.

  • Added a command report verbose that prints additional information such as critical nets.

  • Now exiting with an error if a testbench contains $dumpfile(...) (used to be a warning). Apio sets automatically the location of the dumpfile based on the currently active environment.

  • Apio now defines the macro SYNTHESIZE that allows to simulate modules that use blackbox primitive cells. https://fpgawars.github.io/apio/docs/apio-macros.

  • The project file apio.ini now supports the new option gtkwave-extra-options that allows to customize the invocation of of the signal viewer gtkwave by the apio sim command.

  • Added language support for .pvf, .lpf and .cst FPGA constraint files. This include things such as syntax coloring and block comment/uncomment.

  • The project file apio.ini now supports the option verilator-extra-options which allows to add flags to the verilator commands that apio lint launches.

[0.1.6]

Changed

  • Added support for legacy MacOS/Intel (x86-64)

  • The option 'top-module' is now required in apio.ini. In previous version it was optional with default value 'main'.

[0.1.5]

Cleanup

  • Maintenance release. Streamlined the internal Apio build workflows.

[0.1.4]

Changed

  • Custom boards.jsonc, fpgas.jsonc, and programmers.jsonc definition files are now merged with the standard definitions files instead of replacing them. This allows to use in the same project both standard and custom definitions. In case of a conflict, the custom files win.

  • FPGA constraint files such as pinout.pcf can now be placed also in subdirectories. Previously they had to reside at the top directory of the project. This provides more flexibility in multi-board projects.

[0.1.3]

Initial version.