apio time [OPTIONS]Bitstream timing analysis: generates a rpt file with a topological timing analysis report, from a verilog and constraints files
Required package: oss-cad-suite
| Flag | Long Flag | Description |
|---|---|---|
-b |
--board |
Select a specific board |
--fpga |
Select a specific FPGA | |
--size --type --pack |
Select a specific FPGA size, type and pack | |
-p |
--project-dir |
Set the target directory for the project. |
-v |
--verbose |
Show the entire output of the command |
--verbose-yosys |
Show the yosys output of the command | |
--verbose-pnr |
Show the pnr output of the command | |
--top-module str |
Set the top level module (w/o .v ending) for build |
Note
All available boards, FPGAs, sizes, types and packs are showed in apio boards
apio time
