Commit 33e51f7
fix(BBShiftPanel): prime the SMEM ring before starting a PWM frame
6543a19 moved the self-PWM panel types onto the shared-memory ring along
with the shift panels. The ring delivers every byte - the produced and
consumed counters stay exact and aligned to the PRU's 48 byte load, which
is what that commit verified - but it delivers them late. Measured on
FM6363C hardware, the PRU entered RINGWAIT about seven times per frame for
40-50us each.
That is harmless for a shift panel, where the same PRU drives both the data
and the row address. A self-PWM panel is different: it refreshes from its
own engine while its row scan free runs, so a gap in the shift out lets the
scan walk away from the data. Roughly 300us of gaps per frame against a
~13.8us row period is more than a full pass of drift, which is why the
image slid vertically by a different amount every frame while every
byte-level check came back clean.
The ring was empty at the start of every frame (produced == consumed there),
so the dominant term was the pump's wakeup latency: it polled the frame
sequence on a 500us sleep, and the DATA command went out before any bytes
had been written. So wake the pump from PrepDataPWM rather than having it
poll, hold the DATA command until the pump reports the ring full, and back
off in 20us steps instead of 150us once it is running.
The stall count is unchanged afterwards but every RINGWAIT entry now
resolves on the first reload of the producer counter, so the wait drops
from ~300us per frame to nothing measurable. Checked on 8 and 16 output
capes driving an 80x40 1/10 scan panel. The shift path is untouched and
was re-checked with 64x32 1/16 scan panels on a 16 output cape.
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>1 parent 18bd134 commit 33e51f7
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