fix: update ADMUX at end of ADC ISR to meet ATmega328P timing (#126)

* fix: update ADMUX at end of ADC ISR to meet ATmega328P timing

Move ADMUX write to the end of the ADC_vect ISR so at least 128 CPU cycles
have passed since the trigger event (per ATmega328P datasheet). Prevents
premature channel switching and ensures correct sampling timing.

* #126 (comment)

Author: FredM67

Mk2_3phase_RFdatalog_temp/processing.cpp

@@ -1193,8 +1193,6 @@ ISR(ADC_vect)
 {
   uint16_t adc_raw = ADC;
 
-  ADMUX = _ctx->admux;
-
   if ((_ctx->index & 1) == 0)
   {  // even=voltage, odd=current
     // process voltage channel
@@ -1206,5 +1204,9 @@ ISR(ADC_vect)
     processCurrentRawSample(_ctx->index >> 1, adc_raw);
   }
 
+  // Set ADMUX at the end of the interrupt to ensure at least 128 CPU cycles
+  // have passed since the trigger event (ATmega328p datasheet requirement)
+  ADMUX = _ctx->admux;
+
   _ctx = _ctx->next;
 }  // end of ISR