MiniDXNN/example/kernel/02_texture_training.comp at main · GPUOpen-LibrariesAndSDKs/MiniDXNN · GitHub

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/*!
  \file 02_texture_training.comp
  \author Sho Ikeda
  \brief HLSL compute kernel for texture generation using MLP
  \copyright Copyright (c) 2026 Advanced Micro Devices, Inc. All Rights Reserved.

  SPDX-License-Identifier: MIT
*/

#include "mlp.hlsl"
#include "texture_training_common.hlsl"
#include "texture_inference_common.hlsl"
#include "optimizer.hlsl"

ByteAddressBuffer UvBuffer;
ByteAddressBuffer TargetBuffer;
ByteAddressBuffer WeightBuffer;
ByteAddressBuffer BiasBuffer;
RWByteAddressBuffer WeightGradBuffer;
RWByteAddressBuffer BiasGradBuffer;
RWByteAddressBuffer LogitsCacheBuffer;
RWByteAddressBuffer LossBuffer;
RWByteAddressBuffer RWWeightBuffer;
RWByteAddressBuffer RWBiasBuffer;
RWByteAddressBuffer OutputBuffer;
RWByteAddressBuffer WeightFirstMoment;
RWByteAddressBuffer WeightSecondMoment;
RWByteAddressBuffer BiasFirstMoment;
RWByteAddressBuffer BiasSecondMoment;
int TEST_WEIGHT_MATRIX_SIZE_FIRST;
int TEST_WEIGHT_MATRIX_SIZE_HIDDEN;
int TEST_CURRENT_BATCH_SIZE;
int TEST_BATCH_INDEX;
int TEST_BIAS_STRIDE;
int TEST_NUM_INFERENCE_TASKS;
int OptimizerTimestep;

// ============================================================================
// Training kernel
// ============================================================================

template <typename Type>
void training(const uint threadId)
{
  const dx::linalg::ComponentEnum elemType = mininn::impl::TypeTraits<Type>::COMPONENT_TYPE;
  const dx::linalg::MatrixLayoutEnum layout = (dx::linalg::MatrixLayoutEnum)MINIDXNN_WEIGHT_MATRIX_LAYOUT;
  using ActivationHiddenT = mininn:: MINIDXNN_ACTIVATION_HIDDEN_TYPE;
  using ActivationLastT = mininn:: MINIDXNN_ACTIVATION_LAST_TYPE;

  texkernel::trainingStep<Type, MINIDXNN_NUM_LAYERS, MINIDXNN_HIDDEN_LAYER_DIMENSIONS,
      elemType, layout, ActivationHiddenT, ActivationLastT,
      MINIDXNN_WEIGHT_MATRIX_ALIGNMENT, MINIDXNN_WEIGHT_MATRIX_VECTOR_STRIDE_ALIGNMENT, MINIDXNN_BIAS_VECTOR_ALIGNMENT>(
      threadId, UvBuffer, TargetBuffer, WeightBuffer, BiasBuffer,
      WeightGradBuffer, BiasGradBuffer, LogitsCacheBuffer, LossBuffer,
      uint2((uint)TEST_WEIGHT_MATRIX_SIZE_FIRST, (uint)TEST_WEIGHT_MATRIX_SIZE_HIDDEN),
      MINIDXNN_BATCH_SIZE, (uint)TEST_BATCH_INDEX, (uint)TEST_CURRENT_BATCH_SIZE, (uint)TEST_BIAS_STRIDE);
}

// ============================================================================
// Optimizer kernels
// ============================================================================

template <typename Type>
void sgdStep(const uint threadId)
{
  const uint wTotal = MINIDXNN_WEIGHT_BUFFER_SIZE / (uint)sizeof(Type);
  const uint bTotal = MINIDXNN_BIAS_BUFFER_SIZE / (uint)sizeof(Type);
  optimizer::sgdElement<Type>(RWWeightBuffer, WeightGradBuffer, (float)MINIDXNN_LEARNING_RATE, 1.0f, threadId, wTotal);
  optimizer::sgdElement<Type>(RWBiasBuffer, BiasGradBuffer, (float)MINIDXNN_LEARNING_RATE, 1.0f, threadId, bTotal);
}

template <typename Type>
void adamStep(const uint threadId)
{
  const uint wTotal = MINIDXNN_WEIGHT_BUFFER_SIZE / (uint)sizeof(Type);
  const uint bTotal = MINIDXNN_BIAS_BUFFER_SIZE / (uint)sizeof(Type);
  const float bc1 = 1.0f - pow(MINIDXNN_OPTIMIZER_BETA1, (float)OptimizerTimestep);
  const float bc2 = 1.0f - pow(MINIDXNN_OPTIMIZER_BETA2, (float)OptimizerTimestep);
  optimizer::adamElement<Type>(RWWeightBuffer, WeightGradBuffer,
      WeightFirstMoment, WeightSecondMoment,
      (float)MINIDXNN_LEARNING_RATE,
      MINIDXNN_OPTIMIZER_BETA1, MINIDXNN_OPTIMIZER_BETA2, MINIDXNN_OPTIMIZER_EPSILON,
      bc1, bc2, 1.0f, threadId, wTotal);
  optimizer::adamElement<Type>(RWBiasBuffer, BiasGradBuffer,
      BiasFirstMoment, BiasSecondMoment,
      (float)MINIDXNN_LEARNING_RATE,
      MINIDXNN_OPTIMIZER_BETA1, MINIDXNN_OPTIMIZER_BETA2, MINIDXNN_OPTIMIZER_EPSILON,
      bc1, bc2, 1.0f, threadId, bTotal);
}

template <typename Type>
void lionStep(const uint threadId)
{
  const uint wTotal = MINIDXNN_WEIGHT_BUFFER_SIZE / (uint)sizeof(Type);
  const uint bTotal = MINIDXNN_BIAS_BUFFER_SIZE / (uint)sizeof(Type);
  optimizer::lionElement<Type>(RWWeightBuffer, WeightGradBuffer,
      WeightFirstMoment,
      (float)MINIDXNN_LEARNING_RATE,
      MINIDXNN_OPTIMIZER_BETA1, MINIDXNN_OPTIMIZER_BETA2,
      MINIDXNN_OPTIMIZER_WEIGHT_DECAY,
      1.0f, threadId, wTotal);
  optimizer::lionElement<Type>(RWBiasBuffer, BiasGradBuffer,
      BiasFirstMoment,
      (float)MINIDXNN_LEARNING_RATE,
      MINIDXNN_OPTIMIZER_BETA1, MINIDXNN_OPTIMIZER_BETA2,
      MINIDXNN_OPTIMIZER_WEIGHT_DECAY,
      1.0f, threadId, bTotal);
}

// ============================================================================
// Inference kernel (for texture reconstruction after training)
// ============================================================================

template <typename Type>
void inference(const uint threadId)
{
  const dx::linalg::ComponentEnum elemType = mininn::impl::TypeTraits<Type>::COMPONENT_TYPE;
  const dx::linalg::MatrixLayoutEnum layout = (dx::linalg::MatrixLayoutEnum)MINIDXNN_WEIGHT_MATRIX_LAYOUT;
  using ActivationHiddenT = mininn:: MINIDXNN_ACTIVATION_HIDDEN_TYPE;
  using ActivationLastT = mininn:: MINIDXNN_ACTIVATION_LAST_TYPE;

  texkernel::inferenceStep<Type, MINIDXNN_NUM_LAYERS, MINIDXNN_HIDDEN_LAYER_DIMENSIONS,
      elemType, layout, ActivationHiddenT, ActivationLastT,
      MINIDXNN_WEIGHT_MATRIX_ALIGNMENT, MINIDXNN_WEIGHT_MATRIX_VECTOR_STRIDE_ALIGNMENT, MINIDXNN_BIAS_VECTOR_ALIGNMENT,
      (MINIDXNN_HAS_BIAS != 0)>(
      threadId, UvBuffer, OutputBuffer, WeightBuffer, BiasBuffer,
      uint2((uint)TEST_WEIGHT_MATRIX_SIZE_FIRST, (uint)TEST_WEIGHT_MATRIX_SIZE_HIDDEN),
      (uint)TEST_NUM_INFERENCE_TASKS);
}

// ============================================================================
// Kernel entry points
// ============================================================================

[numthreads(MINIDXNN_NUM_THREADS_X, 1, 1)]
void trainingF32Kernel(const uint3 groupThreadId : SV_GroupThreadID, const uint3 groupId : SV_GroupID)
{
  const uint threadId = groupId.x * MINIDXNN_NUM_THREADS_X + groupThreadId.x;
  training<float>(threadId);
}

[numthreads(MINIDXNN_NUM_THREADS_X, 1, 1)]
void trainingF16Kernel(const uint3 groupThreadId : SV_GroupThreadID, const uint3 groupId : SV_GroupID)
{
  const uint threadId = groupId.x * MINIDXNN_NUM_THREADS_X + groupThreadId.x;
  training<half>(threadId);
}

[numthreads(MINIDXNN_NUM_THREADS_X, 1, 1)]
void sgdStepF32Kernel(const uint3 groupThreadId : SV_GroupThreadID, const uint3 groupId : SV_GroupID)
{
  const uint threadId = groupId.x * MINIDXNN_NUM_THREADS_X + groupThreadId.x;
  sgdStep<float32_t>(threadId);
}

[numthreads(MINIDXNN_NUM_THREADS_X, 1, 1)]
void sgdStepF16Kernel(const uint3 groupThreadId : SV_GroupThreadID, const uint3 groupId : SV_GroupID)
{
  const uint threadId = groupId.x * MINIDXNN_NUM_THREADS_X + groupThreadId.x;
  sgdStep<float16_t>(threadId);
}

[numthreads(MINIDXNN_NUM_THREADS_X, 1, 1)]
void adamStepF32Kernel(const uint3 groupThreadId : SV_GroupThreadID, const uint3 groupId : SV_GroupID)
{
  const uint threadId = groupId.x * MINIDXNN_NUM_THREADS_X + groupThreadId.x;
  adamStep<float32_t>(threadId);
}

[numthreads(MINIDXNN_NUM_THREADS_X, 1, 1)]
void adamStepF16Kernel(const uint3 groupThreadId : SV_GroupThreadID, const uint3 groupId : SV_GroupID)
{
  const uint threadId = groupId.x * MINIDXNN_NUM_THREADS_X + groupThreadId.x;
  adamStep<float16_t>(threadId);
}

[numthreads(MINIDXNN_NUM_THREADS_X, 1, 1)]
void lionStepF32Kernel(const uint3 groupThreadId : SV_GroupThreadID, const uint3 groupId : SV_GroupID)
{
  const uint threadId = groupId.x * MINIDXNN_NUM_THREADS_X + groupThreadId.x;
  lionStep<float32_t>(threadId);
}

[numthreads(MINIDXNN_NUM_THREADS_X, 1, 1)]
void lionStepF16Kernel(const uint3 groupThreadId : SV_GroupThreadID, const uint3 groupId : SV_GroupID)
{
  const uint threadId = groupId.x * MINIDXNN_NUM_THREADS_X + groupThreadId.x;
  lionStep<float16_t>(threadId);
}

[numthreads(MINIDXNN_NUM_THREADS_X, 1, 1)]
void inferenceF32Kernel(const uint3 groupThreadId : SV_GroupThreadID, const uint3 groupId : SV_GroupID)
{
  const uint threadId = groupId.x * MINIDXNN_NUM_THREADS_X + groupThreadId.x;
  inference<float>(threadId);
}

[numthreads(MINIDXNN_NUM_THREADS_X, 1, 1)]
void inferenceF16Kernel(const uint3 groupThreadId : SV_GroupThreadID, const uint3 groupId : SV_GroupID)
{
  const uint threadId = groupId.x * MINIDXNN_NUM_THREADS_X + groupThreadId.x;
  inference<half>(threadId);
}