Unsupported opcode 9C STZ in Tiny64

[tingtron]

This seems to be a common opcode, but gives an error in Tiby64.

STZ Store Zero in Memory

[GeorgRottensteiner]

Ah, thanks for catching that!
Tiny64 only supports the 6510 for now. But I should handle that more gracefully.

[tingtron]

No, the error message seems to be fine, and it continues after that.

However, the support of the common 6502 family opcodes could be helpful for Tiny64, since C64Studio it's used for x16 and Mega65.
Also it would be great for people learning and prototyping Assembly.

I didn't realize that there were actually a small set of new instructions. Many of them are just convenience and re-use existing functionality.

Would it be feasible if Tiny64 had "modes" (6510 and 65c02)? -- If someone offers to provide implementation for the missing instructions.

[tingtron]

What other opcodes introduced in 65C02 are missing from 6510?

The 65C02 introduced several new instructions and addressing modes that are not present in the 6502 or its derivatives like the 6510.

Here's a breakdown of the additional opcodes and addressing modes:

1. Additional Addressing Modes for Existing Instructions

   ADC, AND, CMP, EOR, LDA, ORA, SBC, STA (zp): Adds a zero-page indirect addressing mode, which is faster than (zp),Y when Y is zero.
   BIT (imm, abs,X, zp,X): Expands the BIT instruction with immediate, absolute indexed, and zero-page indexed addressing modes.

2. New Instructions

   BRA (Branch Always): An unconditional branch instruction that uses a single-byte relative address, potentially saving a byte of code compared to JMP.
   INC A, DEC A (Increment/Decrement Accumulator): New instructions to increment or decrement the accumulator, which was an oversight in the original 6502 instruction set.
   JMP (abs,X): A new addressing mode for JMP that allows jumping to an address pointed to by an indexed absolute address, useful for jump tables.
   PHX, PLX, PHY, PLY (Push/Pull X/Y Registers): Instructions for pushing and pulling the X and Y registers to and from the stack, simplifying the saving and restoring of these registers.
   STZ (Store Zero): As discussed, this instruction efficiently stores a zero value in memory without affecting the accumulator.
   TRB (Test and Reset Bits): Tests a memory location against the accumulator and clears bits in the memory location where corresponding accumulator bits are set. It's similar to BIT, but also modifies memory.
   TSB (Test and Set Bits): Similar to TRB, but sets bits in the memory location where corresponding accumulator bits are set.

3. Rockwell and Western Design Center (WDC) specific additions

   BBR, BBS (Branch on Bit Reset/Set): These instructions test a specific bit in a zero-page memory location and branch accordingly. They are only available on 65C02s manufactured by Rockwell and WDC.
   RMB, SMB (Reset/Set Memory Bit): These instructions clear or set a specific bit in a zero-page memory location. Again, they are specific to Rockwell and WDC versions of the 65C02.
   STP (Stop the Processor): Available on WDC 65C02s, this instruction stops the CPU until a hardware reset occurs, putting the processor in a low-power state.
   WAI (Wait for Interrupt): Also on WDC 65C02s, this instruction puts the CPU in a low-power state until an interrupt occurs, ensuring the interrupt is recognized immediately.

These added opcodes and addressing modes offered improved efficiency, particularly for tasks like zeroing memory, working with bitfields, and handling interrupts, making the 65C02 a more versatile and powerful processor compared to the 6502/6510.

[GeorgRottensteiner]

Yeah, there are quite a lot. They unfortunately overlap on different architectures. That will require a bigger change to add all supported processors. C64Studio also does Z80 and 68000 among others, which are wildly different.
Making the basic processors work for simple debugging is also one thing, basically making emulators for all of them will be a mammoth task :)
My long term wish is to add that, but the week has only so many days.. I can't promise anything.