This repository contains the source code and testbenches for the Complete Bridge project, which implements and verifies an AXI-to-Wishbone and Wishbone-to-AXI bridge and associated peripherals.
The project aims to design a bidirectional bridge between the AXI and Wishbone bus protocols. This allows communication and interoperability between modules using different bus interfaces in FPGA-based SoCs.
The repository includes:
- Verilog source files for the AXI-Wishbone bridge (
complete_bridge.v) and related modules. - Testbenches for functional verification of the bridge and peripherals.
- Simulation scripts and configuration files for running the testbenches.
- A dummy Wishbone memory and AXI ip model for simulation and verification.
- Vivado project files (excluded from GitHub via
.gitignore).
Complete_bridge_testing/ │ ├── AXI2WB_bridge test.srcs/ # Source files and testbenches ├── AXI2WB_bridge test.sim/ # Simulation output files (ignored by Git) ├── vivado.jou, vivado.log, etc. # Vivado logs (ignored by Git) ├── complete_bridge.v # Top-level bridge module ├── wb_intercon.v # Wishbone interconnect module ├── README.md # This file ├── .gitignore # Git ignore rules for Vivado and simulation files └── ... # Other project files and directories
- Xilinx Vivado Design Suite (for synthesis and implementation)
- Verilog simulator (e.g., ModelSim, VCS, or XSIM)
- Git (for version control)
- Open the Vivado project (if applicable).
- Run the provided testbenches in your preferred simulator.
- Verify the waveforms and output logs to ensure correct bridge behavior.
Use Vivado GUI or TCL scripts to synthesize the design and generate the bitstream for your FPGA board.
Feel free to fork this repository, make improvements, and submit pull requests.