feat: Rust 2024 edition (#309)

* feat: Rust `2024` edition

* fix: remind assembler its still riscv64gc

This is a workaround for rust-lang/rust#80608

* fmt

* fmt

* remove expects

* Update Cargo.toml

Author: JonasKruckenberg

Cargo.toml

@@ -4,26 +4,14 @@ resolver = "2"
 
 [workspace.package]
 version = "0.1.0"
-edition = "2021"
+edition = "2024"
 authors = ["Jonas Kruckenberg <[email protected]>"]
 license = "MIT OR Apache-2.0"
 
 [workspace.lints.rust]
-rust-2024-compatibility = "deny"
-if_let_rescope = "allow"
-
 # allow loom
 unexpected_cfgs = { level = "warn", check-cfg = ['cfg(loom)'] }
 
-#keyword_idents_2024 = 'warn'
-#unsafe-attr-outside-unsafe = 'warn'
-#deprecated-safe-2024 = 'warn'
-#rust-2024-guarded-string-incompatible-syntax = 'warn'
-#rust-2024-prelude-collisions = 'warn'
-#rust-2024-incompatible-pat = 'warn'
-#missing-unsafe-on-extern = 'warn'
-#impl-trait-overcaptures = 'warn'
-
 [workspace.lints.clippy]
 # numeric safety
 #arithmetic_side_effects = "deny" TODO audit arithmetic & reenable

flake.lock

@@ -6,7 +6,7 @@
 // copied, modified, or distributed except according to those terms.
 
 use crate::vm::bootstrap_alloc::BootstrapAllocator;
-use crate::{arch, INITIAL_HEAP_SIZE_PAGES};
+use crate::{INITIAL_HEAP_SIZE_PAGES, arch};
 use core::alloc::Layout;
 use core::range::Range;
 use loader_api::BootInfo;

kernel/src/allocator.rs

@@ -16,11 +16,11 @@
 //! - `with_user_memory_access` for temporarily enabling kernel access to userspace memory
 //! - `mb`, `rmb`, `wmb` for memory barriers
 //! - `set_thread_ptr`, `get_stack_pointer`, `get_next_older_pc_from_fp`, `assert_fp_is_aligned` for
-//!     WASM stack support
+//!   WASM stack support
 //! - `device::cpu::init`, `device::cpu::with_cpu_info` for CPU initialization
 //! - `invalidate_range`, `is_kernel_address`, `AddressSpace`, `KERNEL_ASPACE_BASE`,
-//!     `USER_ASPACE_BASE`, `PAGE_SHIFT`, `CANONICAL_ADDRESS_MASK`, `PAGE_SIZE`, `DEFAULT_ASID` to
-//!      support the virtual memory subsystem
+//!   `USER_ASPACE_BASE`, `PAGE_SHIFT`, `CANONICAL_ADDRESS_MASK`, `PAGE_SIZE`, `DEFAULT_ASID` to
+//!   support the virtual memory subsystem
 
 cfg_if::cfg_if! {
     if #[cfg(target_arch = "riscv64")] {

kernel/src/arch/mod.rs

@@ -5,13 +5,13 @@
 // http://opensource.org/licenses/MIT>, at your option. This file may not be
 // copied, modified, or distributed except according to those terms.
 
+use crate::CPUID;
 use crate::arch::device;
 use crate::device_tree::DeviceTree;
 use crate::error::Error;
 use crate::irq::InterruptController;
 use crate::time::clock::Ticks;
 use crate::time::{Clock, NANOS_PER_SEC};
-use crate::CPUID;
 use bitflags::bitflags;
 use core::cell::OnceCell;
 use core::str::FromStr;
@@ -82,15 +82,13 @@ pub fn with_cpu<F, R>(f: F) -> R
 where
     F: FnOnce(&Cpu) -> R,
 {
-    #[expect(tail_expr_drop_order, reason = "")]
     CPU.with(|cpu_info| f(cpu_info.get().expect("CPU info not initialized")))
 }
 
 pub fn try_with_cpu<F, R>(f: F) -> Result<R, Error>
 where
     F: FnOnce(&Cpu) -> R,
 {
-    #[expect(tail_expr_drop_order, reason = "")]
     CPU.try_with(|cpu_info| Ok(f(cpu_info.get().ok_or(Error::Uninitialized)?)))?
 }
 

kernel/src/arch/riscv64/device/cpu.rs

@@ -9,11 +9,11 @@ use crate::arch::PAGE_SIZE;
 use crate::device_tree::{Device, DeviceTree, IrqSource};
 use crate::irq::{InterruptController, IrqClaim};
 use crate::vm::{
-    with_kernel_aspace, AddressRangeExt, AddressSpaceRegion, Permissions, PhysicalAddress,
+    AddressRangeExt, AddressSpaceRegion, Permissions, PhysicalAddress, with_kernel_aspace,
 };
 use alloc::string::ToString;
 use core::alloc::Layout;
-use core::mem::{offset_of, MaybeUninit};
+use core::mem::{MaybeUninit, offset_of};
 use core::num::NonZero;
 use core::ops::{BitAnd, BitOr, Not};
 use core::ptr;
@@ -34,8 +34,7 @@ pub struct Plic {
     ndev: usize,
 }
 
-#[repr(packed(4))]
-#[repr(C)]
+#[repr(C, packed(4))]
 struct PlicRegs {
     source_priority: [MmioReg<u32>; 1024], // 0x0000000 -- 0x0000fff
     /// A 32x32 array of 32-bit registers, each representing a bitfield of 1024 pending interrupt bits.
@@ -67,8 +66,7 @@ const_assert_eq!(offset_of!(PlicRegs, pending), 0x001000);
 const_assert_eq!(offset_of!(PlicRegs, enable), 0x002000);
 const_assert_eq!(offset_of!(PlicRegs, thresholds_claims), 0x0200000);
 
-#[repr(packed(4))]
-#[repr(C)]
+#[repr(C, packed(4))]
 struct ThresholdsClaimsRegs {
     threshold: MmioReg<u32>,
     claim_complete: MmioReg<u32>,

kernel/src/arch/riscv64/device/plic.rs

@@ -16,10 +16,10 @@ use crate::vm::VirtualAddress;
 use core::arch::asm;
 use riscv::sstatus::FS;
 use riscv::{interrupt, scounteren, sie, sstatus};
-pub use setjmp_longjmp::{call_with_setjmp, longjmp, JmpBuf};
+pub use setjmp_longjmp::{JmpBuf, call_with_setjmp, longjmp};
 pub use vm::{
-    invalidate_range, is_kernel_address, AddressSpace, CANONICAL_ADDRESS_MASK, DEFAULT_ASID,
-    KERNEL_ASPACE_BASE, PAGE_SHIFT, PAGE_SIZE, USER_ASPACE_BASE,
+    AddressSpace, CANONICAL_ADDRESS_MASK, DEFAULT_ASID, KERNEL_ASPACE_BASE, PAGE_SHIFT, PAGE_SIZE,
+    USER_ASPACE_BASE, invalidate_range, is_kernel_address,
 };
 
 /// Global RISC-V specific initialization.

kernel/src/arch/riscv64/mod.rs

@@ -72,7 +72,7 @@ pub type JmpBuf = *const JmpBufStruct;
 /// This function pretty weird, it can return more than one time:
 /// - The first time it returns, the return value is `0` indicating that the context has been saved.
 /// - Subsequently, calls to `longjmp` that transfer control to the `*mut JumpBuf` used by this `setjmp`
-///     will cause this function to return again, this time with the value passed to `longjmp`.
+///   will cause this function to return again, this time with the value passed to `longjmp`.
 ///
 /// This implementation has been adapted from the [LLVM libc implementation (Apache License v2.0 with LLVM Exceptions)](https://github.com/llvm/llvm-project/blob/bbf2ad026eb0b399364a889799ef6b45878cd299/libc/src/setjmp/riscv/setjmp.cpp)
 ///
@@ -87,6 +87,10 @@ pub unsafe extern "C" fn setjmp(env: JmpBuf) -> i32 {
         cfg_if::cfg_if! {
             if #[cfg(target_feature = "d")] {
                 naked_asm! {
+                    // FIXME this is a workaround for bug in rustc/llvm
+                    //  https://github.com/rust-lang/rust/issues/80608#issuecomment-1094267279
+                    ".attribute arch, \"rv64gc\"",
+
                     save_gp!(ra => a0[0]),
                     save_gp!(s0 => a0[1]),
                     save_gp!(s1 => a0[2]),
@@ -159,6 +163,10 @@ pub unsafe extern "C" fn longjmp(env: JmpBuf, val: i32) -> ! {
         cfg_if::cfg_if! {
             if #[cfg(target_feature = "d")] {
                 naked_asm! {
+                    // FIXME this is a workaround for bug in rustc/llvm
+                    //  https://github.com/rust-lang/rust/issues/80608#issuecomment-1094267279
+                    ".attribute arch, \"rv64gc\"",
+
                     load_gp!(a0[0] => ra),
                     load_gp!(a0[1] => s0),
                     load_gp!(a0[2] => s1),

kernel/src/arch/riscv64/setjmp_longjmp.rs

@@ -6,11 +6,11 @@
 // copied, modified, or distributed except according to those terms.
 
 use super::utils::{define_op, load_fp, load_gp, save_fp, save_gp};
+use crate::TRAP_STACK_SIZE_PAGES;
 use crate::arch::PAGE_SIZE;
 use crate::scheduler::scheduler;
 use crate::traps::TrapReason;
 use crate::vm::VirtualAddress;
-use crate::TRAP_STACK_SIZE_PAGES;
 use core::arch::{asm, naked_asm};
 use cpu_local::cpu_local;
 use riscv::scause::{Exception, Interrupt, Trap};
@@ -85,9 +85,13 @@ unsafe extern "C" fn default_trap_entry() {
     // Safety: inline assembly
     unsafe {
         naked_asm! {
-            ".align 2",
+            // FIXME this is a workaround for bug in rustc/llvm
+            //  https://github.com/rust-lang/rust/issues/80608#issuecomment-1094267279
+            ".attribute arch, \"rv64gc\"",
 
+            ".align 2",
             "csrrw sp, sscratch, sp", // sp points to the TrapFrame
+
             "add sp, sp, -0x210",
 
             // save gp regs
@@ -261,7 +265,9 @@ fn default_trap_handler(
 
     let cause = scause::read().cause();
 
-    tracing::trace!("trap_handler cause {cause:?}, a1 {a1:#x} a2 {a2:#x} a3 {a3:#x} a4 {a4:#x} a5 {a5:#x} a6 {a6:#x} a7 {a7:#x}");
+    tracing::trace!(
+        "trap_handler cause {cause:?}, a1 {a1:#x} a2 {a2:#x} a3 {a3:#x} a4 {a4:#x} a5 {a5:#x} a6 {a6:#x} a7 {a7:#x}"
+    );
     let epc = sepc::read();
     let tval = stval::read();
     tracing::trace!("{:?};epc={epc:#x};tval={tval:#x}", sstatus::read());

kernel/src/arch/riscv64/trap_handler.rs

@@ -6,10 +6,10 @@
 // copied, modified, or distributed except according to those terms.
 
 use crate::arch::{mb, wmb};
+use crate::vm::Error;
 use crate::vm::flush::Flush;
 use crate::vm::frame_alloc::Frame;
-use crate::vm::Error;
-use crate::vm::{frame_alloc, PhysicalAddress, VirtualAddress};
+use crate::vm::{PhysicalAddress, VirtualAddress, frame_alloc};
 use alloc::vec;
 use alloc::vec::Vec;
 use bitflags::bitflags;
@@ -202,7 +202,6 @@ impl crate::vm::ArchAddressSpace for AddressSpace {
             wired_frames: vec![root_pgtable],
         };
 
-        #[expect(tail_expr_drop_order, reason = "")]
         Ok((this, Flush::empty(asid)))
     }
 
@@ -218,7 +217,6 @@ impl crate::vm::ArchAddressSpace for AddressSpace {
             wired_frames: vec![],
         };
 
-        #[expect(tail_expr_drop_order, reason = "")]
         (this, Flush::empty(asid))
     }
 

kernel/src/arch/riscv64/vm.rs

@@ -104,7 +104,6 @@ impl<const MAX_FRAMES: usize> Backtrace<'_, MAX_FRAMES> {
             }
         }
 
-        #[expect(tail_expr_drop_order, reason = "")]
         Ok(Self {
             symbolize_ctx: SYMBOLIZE_CONTEXT.as_ref(),
             frames,

kernel/src/backtrace/mod.rs

@@ -9,7 +9,7 @@ use core::ffi::c_void;
 use core::{fmt, str};
 use fallible_iterator::FallibleIterator;
 use gimli::{EndianSlice, NativeEndian};
-use rustc_demangle::{try_demangle, Demangle};
+use rustc_demangle::{Demangle, try_demangle};
 use xmas_elf::sections::SectionData;
 use xmas_elf::symbol_table::Entry;
 
@@ -192,7 +192,6 @@ impl<'a> SymbolizeContext<'a> {
         })?;
         let addr2line = addr2line::Context::from_dwarf(dwarf)?;
 
-        #[expect(tail_expr_drop_order, reason = "")]
         Ok(Self {
             addr2line,
             elf,
@@ -226,7 +225,6 @@ impl<'a> SymbolizeContext<'a> {
             })
             .unwrap();
 
-        #[expect(tail_expr_drop_order, reason = "")]
         Ok(SymbolsIter {
             addr: probe,
             elf: &self.elf,

kernel/src/backtrace/symbolize.rs

@@ -27,7 +27,6 @@ pub struct Cmdline {
 impl FromStr for Cmdline {
     type Err = Error;
 
-    #[expect(tail_expr_drop_order, reason = "")]
     fn from_str(s: &str) -> Result<Self, Self::Err> {
         let mut log = None;
 

kernel/src/cmdline.rs

@@ -120,11 +120,8 @@ impl<T: Send> CpuLocal<T> {
     where
         F: FnOnce() -> T,
     {
-        #[expect(tail_expr_drop_order, reason = "")]
         // Safety: value will be initialized by `create` if necessary
-        unsafe {
-            self.get_or_try(|| Ok::<T, ()>(create())).unwrap_unchecked()
-        }
+        unsafe { self.get_or_try(|| Ok::<T, ()>(create())).unwrap_unchecked() }
     }
 
     /// Returns the element for the current cpu, or creates it if it doesn't
@@ -141,7 +138,6 @@ impl<T: Send> CpuLocal<T> {
             return Ok(val);
         }
 
-        #[expect(tail_expr_drop_order, reason = "")]
         Ok(self.insert(cpuid, create()?))
     }
 

kernel/src/cpu_local.rs

@@ -12,7 +12,7 @@ use core::{fmt, iter, mem, slice};
 use fallible_iterator::FallibleIterator;
 use fdt::{CellSizes, Error, Fdt, NodeName, StringList};
 use hashbrown::HashMap;
-use smallvec::{smallvec, SmallVec};
+use smallvec::{SmallVec, smallvec};
 use sync::OnceLock;
 
 type Link<T> = Option<NonNull<T>>;
@@ -173,7 +173,6 @@ impl<'a> Device<'a> {
 
     /// Matches the device `compatible` string against the given list of strings.
     pub fn is_compatible<'b>(&self, compats: impl IntoIterator<Item = &'b str>) -> bool {
-        #[expect(tail_expr_drop_order, reason = "")]
         compats.into_iter().any(|c| self.compatible.contains(c))
     }
 
@@ -490,7 +489,6 @@ pub fn init(fdt: &[u8]) -> crate::Result<&'static DeviceTree> {
                 stack[depth] = Some(ptr);
             }
 
-            #[expect(tail_expr_drop_order, reason = "")]
             Ok(DeviceTreeInner { phandle2ptr, root })
         })
     })

kernel/src/device_tree.rs

@@ -13,7 +13,7 @@
 #![feature(new_range_api)]
 #![feature(debug_closure_helpers)]
 #![expect(internal_features, reason = "panic internals")]
-#![feature(std_internals, panic_can_unwind, fmt_internals)]
+#![feature(std_internals, panic_can_unwind, formatting_options)]
 #![feature(step_trait)]
 #![feature(box_into_inner)]
 #![feature(let_chains)]
@@ -23,7 +23,6 @@
 #![feature(if_let_guard)]
 #![feature(allocator_api)]
 #![expect(dead_code, reason = "TODO")] // TODO remove
-#![expect(edition_2024_expr_fragment_specifier, reason = "vetted")]
 
 extern crate alloc;
 
@@ -50,8 +49,8 @@ mod wasm;
 
 use crate::device_tree::device_tree;
 use crate::error::Error;
-use crate::time::clock::Ticks;
 use crate::time::Instant;
+use crate::time::clock::Ticks;
 use crate::vm::bootstrap_alloc::BootstrapAllocator;
 use arrayvec::ArrayVec;
 use cfg_if::cfg_if;
@@ -63,8 +62,8 @@ use loader_api::{BootInfo, LoaderConfig, MemoryRegionKind};
 use rand::SeedableRng;
 use rand_chacha::ChaCha20Rng;
 use sync::Once;
-use vm::frame_alloc;
 use vm::PhysicalAddress;
+use vm::frame_alloc;
 
 /// The size of the stack in pages
 pub const STACK_SIZE_PAGES: u32 = 256; // TODO find a lower more appropriate value