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aarch64/fenv: fix fenv_t (#319)
* aarch64: copy `aarch64/fenv.h` from FreeBSD https://github.com/freebsd/freebsd-src/blob/de1aa3dab23c06fec962a14da3e7b4755c5880cf/lib/msun/aarch64/fenv.h * aarch64: clean code * arm: remove AARCH64 ifdef
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‎include/openlibm_fenv.h

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@@ -2,7 +2,9 @@
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#include <fenv.h>
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#else /* !OPENLIBM_USE_HOST_FENV_H */
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5-
#if defined(__aarch64__) || defined(__arm__)
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#if defined(__aarch64__)
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#include <openlibm_fenv_aarch64.h>
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#elif defined(__arm__)
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#include <openlibm_fenv_arm.h>
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#elif defined(__x86_64__)
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#include <openlibm_fenv_amd64.h>

‎include/openlibm_fenv_aarch64.h

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@@ -0,0 +1,247 @@
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/*-
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* Copyright (c) 2004-2005 David Schultz <[email protected]>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _FENV_H_
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#define _FENV_H_
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#include <stdint.h>
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#include "cdefs-compat.h"
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#ifndef __fenv_static
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#define __fenv_static static
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#endif
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/* The high 32 bits contain fpcr, low 32 contain fpsr. */
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typedef __uint64_t fenv_t;
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typedef __uint64_t fexcept_t;
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/* Exception flags */
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#define FE_INVALID 0x00000001
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#define FE_DIVBYZERO 0x00000002
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#define FE_OVERFLOW 0x00000004
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#define FE_UNDERFLOW 0x00000008
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#define FE_INEXACT 0x00000010
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#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
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FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
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/*
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* Rounding modes
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*
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* We can't just use the hardware bit values here, because that would
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* make FE_UPWARD and FE_DOWNWARD negative, which is not allowed.
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*/
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#define FE_TONEAREST 0x0
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#define FE_UPWARD 0x1
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#define FE_DOWNWARD 0x2
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#define FE_TOWARDZERO 0x3
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#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \
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FE_UPWARD | FE_TOWARDZERO)
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#define _ROUND_SHIFT 22
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__BEGIN_DECLS
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/* Default floating-point environment */
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extern const fenv_t __fe_dfl_env;
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#define FE_DFL_ENV (&__fe_dfl_env)
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/* We need to be able to map status flag positions to mask flag positions */
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#define _FPUSW_SHIFT 8
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#define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT)
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#define __mrs_fpcr(__r) __asm __volatile("mrs %0, fpcr" : "=r" (__r))
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#define __msr_fpcr(__r) __asm __volatile("msr fpcr, %0" : : "r" (__r))
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#define __mrs_fpsr(__r) __asm __volatile("mrs %0, fpsr" : "=r" (__r))
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#define __msr_fpsr(__r) __asm __volatile("msr fpsr, %0" : : "r" (__r))
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__fenv_static inline int
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feclearexcept(int __excepts)
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{
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fexcept_t __r;
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__mrs_fpsr(__r);
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__r &= ~__excepts;
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__msr_fpsr(__r);
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return (0);
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}
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__fenv_static inline int
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fegetexceptflag(fexcept_t *__flagp, int __excepts)
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{
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fexcept_t __r;
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__mrs_fpsr(__r);
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*__flagp = __r & __excepts;
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return (0);
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}
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__fenv_static inline int
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fesetexceptflag(const fexcept_t *__flagp, int __excepts)
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{
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fexcept_t __r;
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__mrs_fpsr(__r);
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__r &= ~__excepts;
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__r |= *__flagp & __excepts;
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__msr_fpsr(__r);
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return (0);
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}
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__fenv_static inline int
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feraiseexcept(int __excepts)
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{
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fexcept_t __r;
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__mrs_fpsr(__r);
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__r |= __excepts;
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__msr_fpsr(__r);
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return (0);
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}
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__fenv_static inline int
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fetestexcept(int __excepts)
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{
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fexcept_t __r;
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__mrs_fpsr(__r);
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return (__r & __excepts);
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}
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__fenv_static inline int
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fegetround(void)
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{
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fenv_t __r;
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__mrs_fpcr(__r);
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return ((__r >> _ROUND_SHIFT) & _ROUND_MASK);
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}
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__fenv_static inline int
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fesetround(int __round)
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{
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fenv_t __r;
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if (__round & ~_ROUND_MASK)
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return (-1);
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__mrs_fpcr(__r);
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__r &= ~(_ROUND_MASK << _ROUND_SHIFT);
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__r |= __round << _ROUND_SHIFT;
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__msr_fpcr(__r);
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return (0);
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}
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__fenv_static inline int
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fegetenv(fenv_t *__envp)
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{
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__uint64_t fpcr;
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__uint64_t fpsr;
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__mrs_fpcr(fpcr);
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__mrs_fpsr(fpsr);
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*__envp = fpsr | (fpcr << 32);
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return (0);
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}
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__fenv_static inline int
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feholdexcept(fenv_t *__envp)
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{
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fenv_t __r;
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__mrs_fpcr(__r);
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*__envp = __r << 32;
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__r &= ~(_ENABLE_MASK);
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__msr_fpcr(__r);
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__mrs_fpsr(__r);
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*__envp |= (__uint32_t)__r;
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__r &= ~(_ENABLE_MASK);
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__msr_fpsr(__r);
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return (0);
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}
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__fenv_static inline int
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fesetenv(const fenv_t *__envp)
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{
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__msr_fpcr((*__envp) >> 32);
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__msr_fpsr((fenv_t)(__uint32_t)*__envp);
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return (0);
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}
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__fenv_static inline int
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feupdateenv(const fenv_t *__envp)
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{
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fexcept_t __r;
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__mrs_fpsr(__r);
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fesetenv(__envp);
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feraiseexcept(__r & FE_ALL_EXCEPT);
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return (0);
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}
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#if __BSD_VISIBLE
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/* We currently provide no external definitions of the functions below. */
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static inline int
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feenableexcept(int __mask)
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{
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fenv_t __old_r, __new_r;
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__mrs_fpcr(__old_r);
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__new_r = __old_r | ((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT);
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__msr_fpcr(__new_r);
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return ((__old_r >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
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}
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static inline int
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fedisableexcept(int __mask)
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{
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fenv_t __old_r, __new_r;
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__mrs_fpcr(__old_r);
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__new_r = __old_r & ~((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT);
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__msr_fpcr(__new_r);
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return ((__old_r >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
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}
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static inline int
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fegetexcept(void)
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{
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fenv_t __r;
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__mrs_fpcr(__r);
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return ((__r & _ENABLE_MASK) >> _FPUSW_SHIFT);
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}
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#endif /* __BSD_VISIBLE */
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__END_DECLS
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#endif /* !_FENV_H_ */

‎include/openlibm_fenv_arm.h

+1-4
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@@ -66,12 +66,9 @@ extern const fenv_t __fe_dfl_env;
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#define _FPUSW_SHIFT 16
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#define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT)
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#if defined(__aarch64__)
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#define __rfs(__fpsr) __asm __volatile("mrs %0,fpsr" : "=r" (*(__fpsr)))
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#define __wfs(__fpsr) __asm __volatile("msr fpsr,%0" : : "r" (__fpsr))
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/* Test for hardware support for ARM floating point operations, explicitly
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checking for float and double support, see "ARM C Language Extensions", 6.5.1 */
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#elif defined(__ARM_FP) && (__ARM_FP & 0x0C) != 0
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#if defined(__ARM_FP) && (__ARM_FP & 0x0C) != 0
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#define __rfs(__fpsr) __asm __volatile("vmrs %0,fpscr" : "=&r" (*(__fpsr)))
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#define __wfs(__fpsr) __asm __volatile("vmsr fpscr,%0" : : "r" (__fpsr))
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#else

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