fenv: fix aarch64 fenv_t

Author: inkydragon

aarch64/fenv.c

@@ -36,7 +36,10 @@
  * Hopefully the system ID byte is immutable, so it's valid to use
  * this as a default environment.
  */
-const fenv_t __fe_dfl_env = 0;
+const fenv_t __fe_dfl_env = {
+	.__fpcr = 0x0,
+	.__fpsr = 0x0
+};
 
 extern inline int feclearexcept(int __excepts);
 extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts);

include/openlibm_fenv_arm.h

@@ -37,7 +37,28 @@
 #define	__fenv_static	static
 #endif
 
-typedef	uint32_t	fenv_t;
+/* Test Arm Procedure Call Standard */
+#ifdef __ARM_PCS_AAPCS64
+/* AArch64 */
+typedef struct {
+	/** FPCR, Floating-point Control Register
+	 * FPCR is a 64-bit register, but Bits [63:27] is reserved, so we only need 32 bits.
+	 * https://developer.arm.com/documentation/ddi0601/2024-12/AArch64-Registers/FPCR--Floating-point-Control-Register?lang=en
+	 */
+	uint32_t __fpcr;
+	/** FPSR, Floating-point Status Register
+	 * FPSR is a 64-bit register, but Bits [63:32] is reserved, so we only need 32 bits.
+	 * https://developer.arm.com/documentation/ddi0601/2024-12/AArch64-Registers/FPSR--Floating-point-Status-Register?lang=en
+	 */
+	uint32_t __fpsr;
+} fenv_t;
+#else /* AArch32 */
+/** FPSCR, Floating-Point Status and Control Register
+ * FPSCR is a 32-bit register.
+ * https://developer.arm.com/documentation/ddi0601/2024-12/AArch32-Registers/FPSCR--Floating-Point-Status-and-Control-Register?lang=en
+ */
+typedef uint32_t	fenv_t;
+#endif /* __ARM_PCS_AAPCS64 */
 typedef	uint32_t	fexcept_t;
 
 /* Exception flags */