Merge pull request #93 from sdnellen/master

Merge of sdnellen fork

Author: sdnellen

.gitattributes

@@ -0,0 +1,28 @@
+# Handle line endings automatically for files detected as text 
+# and leave all files detected as binary untouched.
+* text=auto
+
+# Never modify line endings of our bash scripts
+*.sh -crlf
+test/** -text
+
+#
+# The above will handle all files NOT found below
+#
+# These files are text and should be normalized (Convert crlf => lf)
+*.css           text
+*.html          text
+*.java          text
+*.js            text
+*.json          text
+*.properties    text
+*.txt           text
+*.xml           text
+
+# These files are binary and should be left untouched
+# (binary is macro for -text -diff)
+*.class         binary
+*.jar           binary
+*.gif           binary
+*.jpg           binary
+*.png           binary

.github/workflows/ci.yaml

@@ -0,0 +1,27 @@
+name: Java CI
+
+on:
+  push:
+    branches:
+      - master
+  pull_request:
+    branches:
+      - master
+
+jobs:
+  build:
+
+    runs-on: ubuntu-latest
+
+    steps:
+    - name: Checkout code
+      uses: actions/checkout@v2
+
+    - name: Set up JDK
+      uses: actions/setup-java@v2
+      with:
+        distribution: 'adopt'
+        java-version: '8'  # Adjust the Java version as needed
+
+    - name: Build with Gradle
+      run: ./gradlew build

.gitignore

@@ -32,6 +32,7 @@ hs_err_pid*
 /test/**/output/
 /test/scripts/test.setup
 /rdl/
+/rdl_local/
 
 # gradle stuff
 /.gradle/

.vscode/launch.json

@@ -0,0 +1,15 @@
+{
+    // Use IntelliSense to learn about possible attributes.
+    // Hover to view descriptions of existing attributes.
+    // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
+    "version": "0.2.0",
+    "configurations": [
+        {
+            "type": "java",
+            "name": "Ordt",
+            "request": "launch",
+            "mainClass": "ordt.extract.Ordt",
+            "projectName": "ordt"
+        }
+    ]
+}

.vscode/settings.json

@@ -0,0 +1,3 @@
+{
+    "java.configuration.updateBuildConfiguration": "automatic"
+}

.vscode/tasks.json

@@ -0,0 +1,19 @@
+{
+	"version": "2.0.0",
+	"tasks": [
+		{
+			"type": "java (build)",
+			"paths": [
+				"${workspace}"
+			],
+			"isFullBuild": true,
+			"group": {
+				"kind": "build",
+				"isDefault": true
+			},
+			"problemMatcher": [],
+			"label": "java (build): Build Workspace",
+			"detail": "$(tools) Build all the Java projects in workspace."
+		}
+	]
+}

README.md

@@ -8,8 +8,9 @@ The tool can generate several outputs from SystemRDL or JSpec, including:
   - SystemVerilog/Verilog RTL code description of registers
   - UVM model of the registers
   - C++ and python models of the registers
+  - C header file providing register address and field defines
   - XML and text file register descriptions
   - SystemRDL and JSpec (conversion)
 
-Easiest way to get started with ordt is to download a runnable jar from the [release area](https://github.com/Juniper/open-register-design-tool/releases).  
-Ordt documentation can be found [here](https://github.com/Juniper/open-register-design-tool/wiki).
+Easiest way to get started with ordt is to download a runnable jar from the [release area](https://github.com/sdnellen/open-register-design-tool/releases).  Older releases can be found at the [Juniper repo release area](https://github.com/Juniper/open-register-design-tool/releases).
+Ordt documentation can be found [here](https://github.com/sdnellen/open-register-design-tool/wiki).

build.gradle

@@ -27,8 +27,8 @@ repositories {
 
 dependencies {
     compile 'org.abego.treelayout:org.abego.treelayout.core:1.0.3'
-    antlr   'org.antlr:antlr4:4.5.1-1'
-    runtime 'org.antlr:antlr4-runtime:4.5.1-1'
+    antlr   'org.antlr:antlr4:4.5.3'
+    runtime 'org.antlr:antlr4-runtime:4.5.3'
 }
 
 final antlrSrc = 'src/ordt/parse/grammars'
@@ -42,7 +42,7 @@ sourceSets {
 		       'src/ordt/extract',
 		       'src/ordt/output',
 		       'src/ordt/parameters',
-		       antlrGen ]
+		       'src/ordt/parse' ]
         }
     	antlr {
     	    srcDirs = [ antlrSrc ]
@@ -70,7 +70,14 @@ compileJava.dependsOn(copyMyDebugController)
 
 generateGrammarSource {
     outputs.upToDateWhen { false }  // force compile of all grammar files so import dependencies are picked up
-//    outputDirectory = file(antlrGen)
+    // copy all generated antlr files to their package locations - not optimum, but avoids ide issues due to package mismatch
+    doLast {
+        final destFolder = 'src'
+        copyAntlrGeneratedFilesToTheirPackages(antlrSrc, 'ExtParms', antlrGen, destFolder)
+        copyAntlrGeneratedFilesToTheirPackages(antlrSrc, 'JSpec', antlrGen, destFolder)
+        copyAntlrGeneratedFilesToTheirPackages(antlrSrc, 'SystemRDL', antlrGen, destFolder)
+        copyAntlrGeneratedFilesToTheirPackages(antlrSrc, 'SimpleSV', antlrGen, destFolder)
+    }
 }
 
 shadowJar {
@@ -99,31 +106,14 @@ task distclean {
     }
 }
 
-// eclipse ide expects java source files to be in directories corresponding to their package.
-// the generateEclipseGrammarSource generates the antlr output and moves output java files into 
-// their respective package directories (note that not all grammars need to be copied)
-task generateEclipseGrammarSource {
-    dependsOn generateGrammarSource
-    doLast {
-        final destFolder = 'src'
-        moveAntlrGeneratedFilesToTheirPackages(antlrSrc, 'ExtParms', antlrGen, destFolder)
-        moveAntlrGeneratedFilesToTheirPackages(antlrSrc, 'JSpec', antlrGen, destFolder)
-        moveAntlrGeneratedFilesToTheirPackages(antlrSrc, 'SystemRDL', antlrGen, destFolder)
-        //moveAntlrGeneratedFilesToTheirPackages(antlrSrc, 'SimpleSVLexer', antlrGen, destFolder)
-        //moveAntlrGeneratedFilesToTheirPackages(antlrSrc, 'SimpleSVParser', antlrGen, destFolder)
-        moveAntlrGeneratedFilesToTheirPackages(antlrSrc, 'SimpleSV', antlrGen, destFolder)
-    }
-}
-
-def moveAntlrGeneratedFilesToTheirPackages(grammarFolder, grammarName, genFolder, destFolder) {
+def copyAntlrGeneratedFilesToTheirPackages(grammarFolder, grammarName, genFolder, destFolder) {
     File grammarFile = file("${grammarFolder}/${grammarName}.g4")
     final grammarPackage = extractPackageNameFromGrammerFile(grammarFile)
     copy {
         from genFolder
         include "${grammarName}*.*"
         into destFolder + "/" + grammarPackage.replaceAll("\\.", "/")
     }
-    project.delete fileTree(genFolder).include("${grammarName}*.*")
 }
 
 def extractPackageNameFromGrammerFile(File grammarFile) {

example.parms

@@ -28,16 +28,16 @@ input rdl {
 output systemverilog {
 	leaf_address_size = 40             // leaf address bits
 	//root_has_leaf_interface = true     // does root module talk directly to leaf  DEPRECATED
-    root_decoder_interface = spi_PIO      // parallel | parallel_pulsed | leaf | serial8 | ring8 | ring16 | ring32 | spi_PIO
+    root_decoder_interface = parallel      // parallel | parallel_pulsed | leaf | serial8 | ring8 | ring16 | ring32 | spi_PIO
     //secondary_decoder_interface = serial8      // parallel | parallel_pulsed | serial8 | ring8 | ring16 | ring32 | spi_PIO | none
     //secondary_base_address = 0x40  // base address as viewed from driver of secondary decoder interface 
     //secondary_low_address = 0x50   // low valid address on secondary decoder interfaces
     //secondary_high_address = 0x5f  // high valid address on secondary decoder interfaces
     //secondary_on_child_addrmaps = true  // add secondary interface to child decoders also
 	base_addr_is_parameter = false     // base address parameter will be added to top module
 	//module_tag = "_version1"         // tag to be added to generated module names
-	//use_gated_logic_clock = false       // use separate gated clock for registers and generate a clk enable output
-	//gated_logic_access_delay = 5     // number of clocks after clk enable before gated logic is accessed
+	use_gated_logic_clock = true       // use separate gated clock for registers and generate a clk enable output
+	gated_logic_access_delay = 2     // number of clocks after clk enable before gated logic is accessed
 	//use_external_select = true         // use an externally generated block select  DEPRECATED
 	block_select_mode = always       // is block select generated internally, externally or always
 	//export_start_end = true           // create addr_start, addr_end outputs 
@@ -61,7 +61,7 @@ output systemverilog {
     //}
     //separate_iwrap_encap_files = true // generate a separate file for each wrap encap (interface/struct) type
     generate_dv_bind_modules = true   // if true generate diagnostic dv bind modules 
-    use_global_dv_bind_controls = true   // if true diagnostic dv bind module settings will be controlled by global packages 
+    use_global_dv_bind_controls = false   // if true diagnostic dv bind module settings will be controlled by global packages 
     //include_addr_monitor = true       // generate io to monitor decoder transactions to a specified address range 
     generate_iwrap_xform_modules = false // generate common wrapper transform modules
     //include_sequential_assign_delays = true // include #1 delay on sequential assigns

rdl_examples/issue_16.rdl

@@ -0,0 +1,23 @@
+// issue 16 debug
+<PARMS>
+output systemverilog {
+    root_decoder_interface = parallel      // parallel | parallel_pulsed | leaf | serial8 | ring8 | ring16 | ring32
+	pulse_intr_on_clear = false    // pulse interrupt output low if any child in intr tree is cleared
+	include_default_coverage = true   // include default cover points in rtl
+    generate_dv_bind_modules = false   // if true generate diagnostic dv bind modules 
+}
+</PARMS>
+
+regfile t_rf {
+        reg {
+            field { reset=1'd0; } fld1 ;
+            field { reset=1'd0; counter; } count1[5] ;
+            field { reset=1'd0; intr; } intr1[5] ;
+        } reg1 ;
+} ;
+
+addrmap {
+        signal {field_reset; activelow;} teser_n;
+        t_rf rf1 @0x0;
+        t_rf rf2 @0x100;
+} basemap;