Skip to content

Cannot run the flow completely #7

Description

@swarnim1694

Hi Furkan,

I am working on Vivado 2021.1 and modified the tcl script so as to create the hardware projects in the said version. The XSA generation was successful and the applications were also built on Vitis 2021.1

First issue I am facing is while building the APP0 it shows error due to multiple reference to variables - time_start, time_delta & t. I am able to build the APP1 successfully though and proceeded with it only while running the ntw app on Cortex A53-0 while APP1 on Cortex A53-1.

Second issue is while running the application on ZCU102 board, I got the menu on the serial terminal and I set the core =1 and initialized the polynomial and also was able to print the polynomial. But after this I am not clear about what flow to follow - will it be direct "Execute code" or will it be "Send polynomial to FPGA" and then "Read polynomial from FPGA" etc. In any case my application is getting stuck in the function "send_eth_data_all" in this line - "while( (read_reg((UINTPTR)(core_config + 1)) & 0x00000001) == 0);"

I also tried with ILA on interfacor 1 module to see the states but the done_read is always high and done_write goes low when I run the "Send polynomial to FPGA command" and s00_axis_tvalid signal is never going high.

Could you please explain the data flow and code flow along with the expected behavior?

Activity

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Metadata

Metadata

Assignees

No one assigned

    Labels

    No labels
    No labels

    Type

    No type

    Projects

    No projects

      Milestone

      No milestone

      Relationships

      None yet

      Development

      No branches or pull requests

      Issue actions