Add asym_dual_port_ram made of sym_dual_port_ram

Author: abarajithan11

deepsocflow/rtl/ext/dual_port_sram.sv

@@ -0,0 +1,20 @@
+module dual_port_sram #(
+    parameter int WIDTH      = 32,
+    parameter int DEPTH      = 256,
+    parameter int ADDR_WIDTH = $clog2(DEPTH)
+)(
+    input  logic                  clk,
+    input  logic                  wen,
+    input  logic [ADDR_WIDTH-1:0] waddr,
+    input  logic [WIDTH-1:0]      din,
+    input  logic                  ren,
+    input  logic [ADDR_WIDTH-1:0] raddr,
+    output logic [WIDTH-1:0]      dout
+);
+    logic [WIDTH-1:0] mem [0:DEPTH-1];
+
+    always_ff @(posedge clk) begin
+        if (wen) mem[waddr] <= din;
+        if (ren) dout       <= mem[raddr];
+    end
+endmodule

deepsocflow/rtl/ext/ram_read_wider.sv

@@ -0,0 +1,51 @@
+`timescale 1ns / 1ps
+
+module asym_ram_sdp_read_wider2 #(
+  parameter int WIDTHA      = 4,
+  parameter int SIZEA       = 1024,
+  parameter int ADDRWIDTHA  = 10,
+  parameter int WIDTHB      = 16,
+  parameter int SIZEB       = 256,
+  parameter int ADDRWIDTHB  = 8
+)(
+  input  logic                  clkA,
+  input  logic                  clkB,   // unused, must be same clk
+  input  logic                  enaA,
+  input  logic                  weA,
+  input  logic                  enaB,
+  input  logic [ADDRWIDTHA-1:0] addrA,  // narrow write addr
+  input  logic [ADDRWIDTHB-1:0] addrB,  // wide read addr
+  input  logic [WIDTHA    -1:0] diA,
+  output logic [WIDTHB    -1:0] doB
+);
+  localparam int RATIO = WIDTHB / WIDTHA;      // assume power-of-2
+  localparam int LOGR  = $clog2(RATIO);
+
+  logic [WIDTHA-1:0] q [RATIO];
+
+  wire [LOGR-1:0]       idx = addrA[LOGR-1:0];
+  wire [ADDRWIDTHB-1:0] row = addrA[ADDRWIDTHA-1:LOGR];
+
+  genvar i;
+  generate
+    for (i = 0; i < RATIO; i++) begin : g
+      dual_port_sram #(
+        .WIDTH(WIDTHA),
+        .DEPTH(SIZEB)
+      ) ram_i (
+        .clk  (clkA),
+        .wen  (enaA && weA && (idx == LOGR'(i))),
+        .waddr(row),
+        .din  (diA),
+        .ren  (enaB),
+        .raddr(addrB),
+        .dout (q[i])
+      );
+    end
+  endgenerate
+
+  always_comb
+    for (int j = 0; j < RATIO; j++)
+      doB[j*WIDTHA +: WIDTHA] = q[j];
+
+endmodule