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abarajithan11abarajithan11
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Fix xsim error, make common register map
1 parent 4c14f38 commit bc3ba41

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4 files changed

+46
-49
lines changed

4 files changed

+46
-49
lines changed

‎deepsocflow/c/runtime.h‎

Lines changed: 5 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -75,16 +75,10 @@ typedef struct {
7575
#define A_X_DONE 0xB
7676
#define A_O_DONE 0xC
7777

78-
#define WB_A_START 0x0
79-
#define WB_A_N_BUNDLES_1 0x1
80-
#define WB_A_EN_COUNT 0x2
81-
#define WB_A_VALID 0x3
82-
#define WB_A_IB 0x4
83-
#define WB_A_IP 0x5
84-
#define WB_A_IN 0x6
85-
#define WB_A_IL 0x7
86-
#define WB_A_IWKW2 0x8
87-
78+
enum wb_reg {
79+
#include "config_reg.def"
80+
WB_A_NUM_REGS
81+
};
8882

8983
#ifdef __cplusplus
9084
#define EXT_C "C"
@@ -93,7 +87,7 @@ typedef struct {
9387
#define EXT_C
9488
#endif
9589
int32_t *p_config = (int32_t *)CONFIG_BASEADDR;
96-
int32_t *p_writeback = p_config + WORDS_IN_CFG;
90+
int32_t *p_writeback = (int32_t *)CONFIG_BASEADDR + WORDS_IN_CFG;
9791

9892
extern EXT_C void model_setup(Memory_st *restrict mp) {
9993

‎deepsocflow/py/hardware.py‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -192,6 +192,19 @@ def export(self):
192192
`define CONFIG_BASEADDR 32'h{self.CONFIG_BASEADDR:<10}
193193
''')
194194

195+
with open('config_reg.def', 'w') as f:
196+
f.write(f'''
197+
WB_A_START = 0,
198+
WB_A_DONE ,
199+
WB_A_N_BUNDLES_1 ,
200+
WB_A_EN_COUNT ,
201+
WB_A_VALID ,
202+
WB_A_IB ,
203+
WB_A_IP ,
204+
WB_A_IN ,
205+
WB_A_IL ,
206+
WB_A_IWKW2 ,
207+
''')
195208

196209
with open('config_hw.tcl', 'w') as f:
197210
f.write(f'''

‎deepsocflow/rtl/writeback.sv‎

Lines changed: 24 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -27,20 +27,17 @@ module writeback #(
2727
);
2828

2929
localparam N_REG = 32;
30-
localparam // Addresses for local memory 0:32 is registers, rest is SRAM
31-
A_START = 'h0,
32-
A_N_BUNDLES_1 = 'h1,
33-
A_EN_COUNT = 'h2,
34-
A_VALID = 'h3,
35-
A_IB = 'h4,
36-
A_IP = 'h5,
37-
A_IN = 'h6,
38-
A_IL = 'h7,
39-
A_IWKW2 = 'h8
40-
; // Max 32 registers
30+
31+
// Addresses for local memory 0:32 is registers, rest is SRAM
32+
typedef enum int {
33+
`include "config_reg.def"
34+
WB_A_NUM_REGS
35+
} wb_reg_e;
36+
4137
logic [WIDTH-1:0] cfg [N_REG-1:0];
42-
wire en_count = 1'(cfg[A_EN_COUNT]);
43-
wire start = 1'(cfg[A_START]);
38+
wire en_count = 1'(cfg[WB_A_EN_COUNT]);
39+
wire start = 1'(cfg[WB_A_START]);
40+
wire [WIDTH-1:0] n_bundles_1 = cfg[WB_A_N_BUNDLES_1];
4441

4542
//------------------- BUNDLES SRAM ---------------------------------------
4643

@@ -69,12 +66,6 @@ module writeback #(
6966
.doB (ram_rd_data)
7067
);
7168

72-
logic [AXI_ADDR_WIDTH-1:0] reg_rd_addr_valid;
73-
always_ff @(posedge clk) begin
74-
ram_rd_valid <= ram_rd_en;
75-
reg_rd_addr_valid <= reg_rd_addr;
76-
end
77-
7869
always_comb begin
7970
ram_wr_en = reg_wr_en && (reg_wr_addr >= N_REG);
8071
ram_wr_addr = SRAM_WR_ADDR_WIDTH'(reg_wr_addr - N_REG);
@@ -103,12 +94,12 @@ module writeback #(
10394
ram_rd_valid <= ram_rd_en;
10495
end
10596

106-
up_counter #(.W(WIDTH)) C_B (.clk(clk), .rstn_g(rstn), .rst_l(start ), .en(lc_p ), .max_in(WIDTH'(cfg[A_N_BUNDLES_1])), .last_clk(lc_b ), .last(l_b ), .first(), .count(i_b ));
107-
up_counter #(.W(WIDTH)) C_P (.clk(clk), .rstn_g(rstn), .rst_l(ram_rd_valid ), .en(lc_t ), .max_in(WIDTH'(ram_max_p )), .last_clk(lc_p ), .last(l_p ), .first(), .count(i_p ));
108-
up_counter #(.W(WIDTH)) C_T (.clk(clk), .rstn_g(rstn), .rst_l(ram_rd_valid ), .en(lc_n ), .max_in(WIDTH'(ram_max_t )), .last_clk(lc_t ), .last(l_t ), .first(), .count(i_t ));
109-
up_counter #(.W(WIDTH)) C_N (.clk(clk), .rstn_g(rstn), .rst_l(ram_rd_valid ), .en(lc_l ), .max_in(WIDTH'(ram_max_n )), .last_clk(lc_n ), .last(l_n ), .first(), .count(i_n ));
110-
up_counter #(.W(WIDTH)) C_L (.clk(clk), .rstn_g(rstn), .rst_l(ram_rd_valid ), .en(lc_wkw2 ), .max_in(WIDTH'(ram_max_l )), .last_clk(lc_l ), .last(l_l ), .first(), .count(i_l ));
111-
up_counter #(.W(WIDTH)) C_WKW2 (.clk(clk), .rstn_g(rstn), .rst_l(ram_rd_valid ), .en(en_count), .max_in(WIDTH'(ram_max_wkw2 )), .last_clk(lc_wkw2), .last(l_wkw2), .first(), .count(i_wkw2));
97+
up_counter #(.W(WIDTH)) C_B (.clk(clk), .rstn_g(rstn), .rst_l(start ), .en(lc_p ), .max_in(n_bundles_1 ), .last_clk(lc_b ), .last(l_b ), .first(), .count(i_b ));
98+
up_counter #(.W(WIDTH)) C_P (.clk(clk), .rstn_g(rstn), .rst_l(ram_rd_valid ), .en(lc_t ), .max_in(ram_max_p ), .last_clk(lc_p ), .last(l_p ), .first(), .count(i_p ));
99+
up_counter #(.W(WIDTH)) C_T (.clk(clk), .rstn_g(rstn), .rst_l(ram_rd_valid ), .en(lc_n ), .max_in(ram_max_t ), .last_clk(lc_t ), .last(l_t ), .first(), .count(i_t ));
100+
up_counter #(.W(WIDTH)) C_N (.clk(clk), .rstn_g(rstn), .rst_l(ram_rd_valid ), .en(lc_l ), .max_in(ram_max_n ), .last_clk(lc_n ), .last(l_n ), .first(), .count(i_n ));
101+
up_counter #(.W(WIDTH)) C_L (.clk(clk), .rstn_g(rstn), .rst_l(ram_rd_valid ), .en(lc_wkw2 ), .max_in(ram_max_l ), .last_clk(lc_l ), .last(l_l ), .first(), .count(i_l ));
102+
up_counter #(.W(WIDTH)) C_WKW2 (.clk(clk), .rstn_g(rstn), .rst_l(ram_rd_valid ), .en(en_count), .max_in(ram_max_wkw2), .last_clk(lc_wkw2), .last(l_wkw2), .first(), .count(i_wkw2));
112103

113104
// It takes a few cycles after en_count for the registers to have valid data:
114105
// 0 - en_count, lc_p
@@ -126,20 +117,19 @@ module writeback #(
126117
end else begin
127118

128119
if (en_count)
129-
cfg[A_EN_COUNT] <= WIDTH'(0);
120+
cfg[WB_A_EN_COUNT] <= WIDTH'(0);
130121

131122
if (start)
132-
cfg[A_START] <= WIDTH'(0);
123+
cfg[WB_A_START] <= WIDTH'(0);
133124

134125
if (i_valid_next)
135-
cfg[A_VALID ] <= WIDTH'(1);
136-
137-
cfg[A_IB ] <= i_b ;
138-
cfg[A_IP ] <= i_p ;
139-
cfg[A_IN ] <= i_n ;
140-
cfg[A_IL ] <= i_l ;
141-
cfg[A_IWKW2 ] <= i_wkw2;
126+
cfg[WB_A_VALID ] <= WIDTH'(1);
142127

128+
cfg[WB_A_IB ] <= i_b ;
129+
cfg[WB_A_IP ] <= i_p ;
130+
cfg[WB_A_IN ] <= i_n ;
131+
cfg[WB_A_IL ] <= i_l ;
132+
cfg[WB_A_IWKW2 ] <= i_wkw2;
143133

144134
if (reg_wr_en && reg_wr_addr < N_REG) // PS has priority in writing to registers
145135
cfg[reg_wr_addr] <= WIDTH'(reg_wr_data);

‎run/param_test.py‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,8 @@
1717

1818
from deepsocflow import *
1919

20-
SIM = 'xsim' if os.name=='nt' else 'verilator'
21-
# SIM = 'xsim'
20+
# SIM = 'xsim' if os.name=='nt' else 'verilator'
21+
SIM = 'xsim'
2222

2323
'''
2424
Dataset
@@ -193,8 +193,8 @@ def product_dict(**kwargs):
193193
axi_width = [ 128 ],
194194
config_baseaddr = ["40000000"],
195195
target_cpu_int_bits = [ 32 ],
196-
valid_prob = [ 0.01 ],
197-
ready_prob = [ 0.05 ],
196+
valid_prob = [ 0.1 ],
197+
ready_prob = [ 0.5 ],
198198
data_dir = ['vectors'],
199199
)))
200200
def test_dnn_engine(PARAMS):

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