From 5537e95befe8ef63be2961e53635aac09ed951ee Mon Sep 17 00:00:00 2001 From: Michal Paszkowski Date: Sun, 26 Mar 2023 20:07:11 +0200 Subject: [PATCH 1/5] [SPIR-V] Remove switch G_ICMP+G_BRCOND+G_BR before ISel IRTranslator lowers switches to [G_SUB] + G_ICMP + G_BRCOND + G_BR sequences. Since values and destination MBBs are included in the spv_switch intrinsics, the sequences are not needed for ISel. Before this commit, the information decoded by these sequences were added to spv_switch intrinsics in SPIRVPreLegalizer and the sequences were kept until SPIRVModuleAnalysis where they were marked skipped for emission. After this commit, the [G_SUB] + G_ICMP + G_BRCOND + G_BR sequences and MBBs containing only these MIs are erased in SPIRVPreLegalizer. --- llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp | 4 +- llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 43 -------------- llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h | 3 - llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 58 ++++++++++++++----- .../{transcoding => branching}/OpSwitch32.ll | 0 .../{transcoding => branching}/OpSwitch64.ll | 0 .../SPIRV/branching/OpSwitchBranches.ll | 41 +++++++++++++ .../OpSwitchChar.ll | 0 .../OpSwitchEmpty.ll | 0 .../OpSwitchUnreachable.ll | 0 .../Two_OpSwitch_same_register.ll | 0 11 files changed, 85 insertions(+), 64 deletions(-) rename llvm/test/CodeGen/SPIRV/{transcoding => branching}/OpSwitch32.ll (100%) rename llvm/test/CodeGen/SPIRV/{transcoding => branching}/OpSwitch64.ll (100%) create mode 100644 llvm/test/CodeGen/SPIRV/branching/OpSwitchBranches.ll rename llvm/test/CodeGen/SPIRV/{transcoding => branching}/OpSwitchChar.ll (100%) rename llvm/test/CodeGen/SPIRV/{transcoding => branching}/OpSwitchEmpty.ll (100%) rename llvm/test/CodeGen/SPIRV/{transcoding => branching}/OpSwitchUnreachable.ll (100%) rename llvm/test/CodeGen/SPIRV/{transcoding => branching}/Two_OpSwitch_same_register.ll (100%) diff --git a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp index 2e822a318ea6..d07c0bcdf9af 100644 --- a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp @@ -134,8 +134,6 @@ void SPIRVAsmPrinter::emitFunctionBodyEnd() { } void SPIRVAsmPrinter::emitOpLabel(const MachineBasicBlock &MBB) { - if (MAI->MBBsToSkip.contains(&MBB)) - return; MCInst LabelInst; LabelInst.setOpcode(SPIRV::OpLabel); LabelInst.addOperand(MCOperand::createReg(MAI->getOrCreateMBBRegister(MBB))); @@ -143,6 +141,8 @@ void SPIRVAsmPrinter::emitOpLabel(const MachineBasicBlock &MBB) { } void SPIRVAsmPrinter::emitBasicBlockStart(const MachineBasicBlock &MBB) { + assert(!MBB.empty() && "MBB is empty!"); + // If it's the first MBB in MF, it has OpFunction and OpFunctionParameter, so // OpLabel should be output after them. if (MBB.getNumber() == MF->front().getNumber()) { diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp index af48d51a056f..22746788607b 100644 --- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp @@ -386,47 +386,6 @@ void SPIRVModuleAnalysis::numberRegistersGlobally(const Module &M) { } } -// Find OpIEqual and OpBranchConditional instructions originating from -// OpSwitches, mark them skipped for emission. Also mark MBB skipped if it -// contains only these instructions. -static void processSwitches(const Module &M, SPIRV::ModuleAnalysisInfo &MAI, - MachineModuleInfo *MMI) { - DenseSet SwitchRegs; - for (auto F = M.begin(), E = M.end(); F != E; ++F) { - MachineFunction *MF = MMI->getMachineFunction(*F); - if (!MF) - continue; - for (MachineBasicBlock &MBB : *MF) - for (MachineInstr &MI : MBB) { - if (MAI.getSkipEmission(&MI)) - continue; - if (MI.getOpcode() == SPIRV::OpSwitch) { - assert(MI.getOperand(0).isReg()); - SwitchRegs.insert(MI.getOperand(0).getReg()); - } - if (MI.getOpcode() == SPIRV::OpISubS && - SwitchRegs.contains(MI.getOperand(2).getReg())) { - SwitchRegs.insert(MI.getOperand(0).getReg()); - MAI.setSkipEmission(&MI); - } - if ((MI.getOpcode() != SPIRV::OpIEqual && - MI.getOpcode() != SPIRV::OpULessThanEqual) || - !MI.getOperand(2).isReg() || - !SwitchRegs.contains(MI.getOperand(2).getReg())) - continue; - Register CmpReg = MI.getOperand(0).getReg(); - MachineInstr *CBr = MI.getNextNode(); - assert(CBr && CBr->getOpcode() == SPIRV::OpBranchConditional && - CBr->getOperand(0).isReg() && - CBr->getOperand(0).getReg() == CmpReg); - MAI.setSkipEmission(&MI); - MAI.setSkipEmission(CBr); - if (&MBB.front() == &MI && &MBB.back() == CBr) - MAI.MBBsToSkip.insert(&MBB); - } - } -} - // RequirementHandler implementations. void SPIRV::RequirementHandler::getAndAddRequirements( SPIRV::OperandCategory::OperandCategory Category, uint32_t i, @@ -1020,8 +979,6 @@ bool SPIRVModuleAnalysis::runOnModule(Module &M) { collectReqs(M, MAI, MMI, *ST); - processSwitches(M, MAI, MMI); - // Process type/const/global var/func decl instructions, number their // destination registers from 0 to N, collect Extensions and Capabilities. processDefInstrs(M); diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h index a8b659ce3957..abb6797c5218 100644 --- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h +++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h @@ -136,9 +136,6 @@ struct ModuleAnalysisInfo { // The set contains machine instructions which are necessary // for correct MIR but will not be emitted in function bodies. DenseSet InstrsToDelete; - // The set contains machine basic blocks which are necessary - // for correct MIR but will not be emitted. - DenseSet MBBsToSkip; // The table contains global aliases of local registers for each machine // function. The aliases are used to substitute local registers during // code emission. diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp index 27d0e8a976f0..1e664ca6cfcd 100644 --- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp @@ -411,19 +411,23 @@ static void processSwitches(MachineFunction &MF, SPIRVGlobalRegistry *GR, // // Sometimes (in case of range-compare switches), additional G_SUBs // instructions are inserted before G_ICMPs. Those need to be additionally - // processed and require type assignment. + // processed. // // This function modifies spv_switch call's operands to include destination // MBBs (default and for each constant value). - // Note that this function does not remove G_ICMP + G_BRCOND + G_BR sequences, - // but they are marked by ModuleAnalysis as skipped and as a result AsmPrinter - // does not output them. + // + // At the end, the function removes redundant [G_SUB] + G_ICMP + G_BRCOND + + // G_BR sequences. MachineRegisterInfo &MRI = MF.getRegInfo(); - // Collect all MIs relevant to switches across all MBBs in MF. + // Collect spv_switches and G_ICMPs across all MBBs in MF. std::vector RelevantInsts; + // Collect redundant MIs from [G_SUB] + G_ICMP + G_BRCOND + G_BR sequences. + // After updating spv_switches, the instructions can be removed. + std::vector PostUpdateArtifacts; + // Temporary set of compare registers. G_SUBs and G_ICMPs relating to // spv_switch use these registers. DenseSet CompareRegs; @@ -443,23 +447,21 @@ static void processSwitches(MachineFunction &MF, SPIRVGlobalRegistry *GR, assert(MI.getOperand(0).isReg() && MI.getOperand(1).isReg()); Register Dst = MI.getOperand(0).getReg(); CompareRegs.insert(Dst); - SPIRVType *Ty = GR->getSPIRVTypeForVReg(MI.getOperand(1).getReg()); - insertAssignInstr(Dst, nullptr, Ty, GR, MIB, MRI); + PostUpdateArtifacts.push_back(&MI); } // G_ICMPs relating to switches. if (MI.getOpcode() == TargetOpcode::G_ICMP && MI.getOperand(2).isReg() && CompareRegs.contains(MI.getOperand(2).getReg())) { Register Dst = MI.getOperand(0).getReg(); - // Set type info for destination register of switch's ICMP instruction. - if (GR->getSPIRVTypeForVReg(Dst) == nullptr) { - MIB.setInsertPt(*MI.getParent(), MI); - Type *LLVMTy = IntegerType::get(MF.getFunction().getContext(), 1); - SPIRVType *SpirvTy = GR->getOrCreateSPIRVType(LLVMTy, MIB); - MRI.setRegClass(Dst, &SPIRV::IDRegClass); - GR->assignSPIRVTypeToVReg(SpirvTy, Dst, MIB.getMF()); - } RelevantInsts.push_back(&MI); + PostUpdateArtifacts.push_back(&MI); + MachineInstr *CBr = MRI.use_begin(Dst)->getParent(); + assert(CBr->getOpcode() == SPIRV::G_BRCOND); + PostUpdateArtifacts.push_back(CBr); + MachineInstr *Br = CBr->getNextNode(); + assert(Br->getOpcode() == SPIRV::G_BR); + PostUpdateArtifacts.push_back(Br); } } } @@ -503,6 +505,9 @@ static void processSwitches(MachineFunction &MF, SPIRVGlobalRegistry *GR, // Map switch case Value to target MBB. ValuesToMBBs[Value] = MBB; + // Add target MBB as successor to the switch's MBB. + Switch->getParent()->addSuccessor(MBB); + // The next MI is always G_BR to either the next case or the default. MachineInstr *NextMI = CBr->getNextNode(); assert(NextMI->getOpcode() == SPIRV::G_BR && @@ -512,8 +517,11 @@ static void processSwitches(MachineFunction &MF, SPIRVGlobalRegistry *GR, // register. if (NextMBB->front().getOpcode() != SPIRV::G_ICMP || (NextMBB->front().getOperand(2).isReg() && - NextMBB->front().getOperand(2).getReg() != CompareReg)) + NextMBB->front().getOperand(2).getReg() != CompareReg)) { + // Set default MBB and add it as successor to the switch's MBB. DefaultMBB = NextMBB; + Switch->getParent()->addSuccessor(DefaultMBB); + } } // Modify considered spv_switch operands using collected Values and @@ -540,6 +548,24 @@ static void processSwitches(MachineFunction &MF, SPIRVGlobalRegistry *GR, Switch->addOperand(MachineOperand::CreateMBB(MBBs[k])); } } + + for (MachineInstr *MI : PostUpdateArtifacts) { + MachineBasicBlock *ParentMBB = MI->getParent(); + MI->eraseFromParent(); + // If G_ICMP + G_BRCOND + G_BR were the only MIs in MBB, erase this MBB. It + // can be safely assumed, there are no breaks or phis directing into this + // MBB. However, we need to remove this MBB from the CFG graph. MBBs must be + // erased top-down. + if (ParentMBB->empty()) { + while (!ParentMBB->pred_empty()) + (*ParentMBB->pred_begin())->removeSuccessor(ParentMBB); + + while (!ParentMBB->succ_empty()) + ParentMBB->removeSuccessor(ParentMBB->succ_begin()); + + ParentMBB->eraseFromParent(); + } + } } bool SPIRVPreLegalizer::runOnMachineFunction(MachineFunction &MF) { diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpSwitch32.ll b/llvm/test/CodeGen/SPIRV/branching/OpSwitch32.ll similarity index 100% rename from llvm/test/CodeGen/SPIRV/transcoding/OpSwitch32.ll rename to llvm/test/CodeGen/SPIRV/branching/OpSwitch32.ll diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpSwitch64.ll b/llvm/test/CodeGen/SPIRV/branching/OpSwitch64.ll similarity index 100% rename from llvm/test/CodeGen/SPIRV/transcoding/OpSwitch64.ll rename to llvm/test/CodeGen/SPIRV/branching/OpSwitch64.ll diff --git a/llvm/test/CodeGen/SPIRV/branching/OpSwitchBranches.ll b/llvm/test/CodeGen/SPIRV/branching/OpSwitchBranches.ll new file mode 100644 index 000000000000..145c43c6da32 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/branching/OpSwitchBranches.ll @@ -0,0 +1,41 @@ +; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV + +define i32 @test_switch_branches(i32 %a) { +entry: + %alloc = alloca i32 +; CHECK-SPIRV: OpSwitch %[[#]] %[[#DEFAULT:]] 1 %[[#CASE1:]] 2 %[[#CASE2:]] 3 %[[#CASE3:]] + switch i32 %a, label %default [ + i32 1, label %case1 + i32 2, label %case2 + i32 3, label %case3 + ] + +; CHECK-SPIRV: %[[#CASE1]] = OpLabel +case1: + store i32 1, ptr %alloc +; CHECK-SPIRV: OpBranch %[[#END:]] + br label %end + +; CHECK-SPIRV: %[[#CASE2]] = OpLabel +case2: + store i32 2, ptr %alloc +; CHECK-SPIRV: OpBranch %[[#END]] + br label %end + +; CHECK-SPIRV: %[[#CASE3]] = OpLabel +case3: + store i32 3, ptr %alloc +; CHECK-SPIRV: OpBranch %[[#END]] + br label %end + +; CHECK-SPIRV: %[[#DEFAULT]] = OpLabel +default: + store i32 0, ptr %alloc +; CHECK-SPIRV: OpBranch %[[#END]] + br label %end + +; CHECK-SPIRV: %[[#END]] = OpLabel +end: + %result = load i32, ptr %alloc + ret i32 %result +} diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpSwitchChar.ll b/llvm/test/CodeGen/SPIRV/branching/OpSwitchChar.ll similarity index 100% rename from llvm/test/CodeGen/SPIRV/transcoding/OpSwitchChar.ll rename to llvm/test/CodeGen/SPIRV/branching/OpSwitchChar.ll diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpSwitchEmpty.ll b/llvm/test/CodeGen/SPIRV/branching/OpSwitchEmpty.ll similarity index 100% rename from llvm/test/CodeGen/SPIRV/transcoding/OpSwitchEmpty.ll rename to llvm/test/CodeGen/SPIRV/branching/OpSwitchEmpty.ll diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpSwitchUnreachable.ll b/llvm/test/CodeGen/SPIRV/branching/OpSwitchUnreachable.ll similarity index 100% rename from llvm/test/CodeGen/SPIRV/transcoding/OpSwitchUnreachable.ll rename to llvm/test/CodeGen/SPIRV/branching/OpSwitchUnreachable.ll diff --git a/llvm/test/CodeGen/SPIRV/transcoding/Two_OpSwitch_same_register.ll b/llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll similarity index 100% rename from llvm/test/CodeGen/SPIRV/transcoding/Two_OpSwitch_same_register.ll rename to llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll From 3c2869d7867041a9e0f1a91beef4efa606751f92 Mon Sep 17 00:00:00 2001 From: Michal Paszkowski Date: Wed, 5 Apr 2023 02:08:31 +0200 Subject: [PATCH 2/5] [SPIR-V] Rename SPIRVGlobalRegistry to SPIRVGlobalTypeRegistry --- llvm/lib/Target/SPIRV/CMakeLists.txt | 2 +- .../SPIRVGlobalTypeRegistry.cpp} | 128 ++--- .../SPIRVGlobalTypeRegistry.h} | 14 +- llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 502 +++++++++--------- llvm/lib/Target/SPIRV/SPIRVBuiltins.h | 8 +- llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp | 44 +- llvm/lib/Target/SPIRV/SPIRVCallLowering.h | 9 +- .../Target/SPIRV/SPIRVInstructionSelector.cpp | 184 +++---- llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp | 16 +- llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.h | 4 +- llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 4 +- llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h | 4 +- llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 82 +-- llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp | 6 +- llvm/lib/Target/SPIRV/SPIRVSubtarget.h | 6 +- llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp | 2 +- 16 files changed, 514 insertions(+), 501 deletions(-) rename llvm/lib/Target/SPIRV/{SPIRVGlobalRegistry.cpp => Registries/SPIRVGlobalTypeRegistry.cpp} (90%) rename llvm/lib/Target/SPIRV/{SPIRVGlobalRegistry.h => Registries/SPIRVGlobalTypeRegistry.h} (97%) diff --git a/llvm/lib/Target/SPIRV/CMakeLists.txt b/llvm/lib/Target/SPIRV/CMakeLists.txt index bcecf141ecdd..23210934db0e 100644 --- a/llvm/lib/Target/SPIRV/CMakeLists.txt +++ b/llvm/lib/Target/SPIRV/CMakeLists.txt @@ -14,12 +14,12 @@ tablegen(LLVM SPIRVGenTables.inc -gen-searchable-tables) add_public_tablegen_target(SPIRVCommonTableGen) add_llvm_target(SPIRVCodeGen + Registries/SPIRVGlobalTypeRegistry.cpp SPIRVAsmPrinter.cpp SPIRVBuiltins.cpp SPIRVCallLowering.cpp SPIRVDuplicatesTracker.cpp SPIRVEmitIntrinsics.cpp - SPIRVGlobalRegistry.cpp SPIRVInstrInfo.cpp SPIRVInstructionSelector.cpp SPIRVISelLowering.cpp diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.cpp similarity index 90% rename from llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp rename to llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.cpp index 062188abbf5e..e2de29162d8c 100644 --- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp +++ b/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.cpp @@ -1,4 +1,4 @@ -//===-- SPIRVGlobalRegistry.cpp - SPIR-V Global Registry --------*- C++ -*-===// +//===-- SPIRVGlobalTypeRegistry.cpp - SPIR-V Global Registry --------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the implementation of the SPIRVGlobalRegistry class, +// This file contains the implementation of the SPIRVGlobalTypeRegistry class, // which is used to maintain rich type information required for SPIR-V even // after lowering from LLVM IR to GMIR. It can convert an llvm::Type into // an OpTypeXXX instruction, and map it to a virtual register. Also it builds @@ -14,7 +14,7 @@ // //===----------------------------------------------------------------------===// -#include "SPIRVGlobalRegistry.h" +#include "SPIRVGlobalTypeRegistry.h" #include "SPIRV.h" #include "SPIRVBuiltins.h" #include "SPIRVSubtarget.h" @@ -22,10 +22,10 @@ #include "SPIRVUtils.h" using namespace llvm; -SPIRVGlobalRegistry::SPIRVGlobalRegistry(unsigned PointerSize) +SPIRVGlobalTypeRegistry::SPIRVGlobalTypeRegistry(unsigned PointerSize) : PointerSize(PointerSize) {} -SPIRVType *SPIRVGlobalRegistry::assignIntTypeToVReg(unsigned BitWidth, +SPIRVType *SPIRVGlobalTypeRegistry::assignIntTypeToVReg(unsigned BitWidth, Register VReg, MachineInstr &I, const SPIRVInstrInfo &TII) { @@ -34,7 +34,7 @@ SPIRVType *SPIRVGlobalRegistry::assignIntTypeToVReg(unsigned BitWidth, return SpirvType; } -SPIRVType *SPIRVGlobalRegistry::assignVectTypeToVReg( +SPIRVType *SPIRVGlobalTypeRegistry::assignVectTypeToVReg( SPIRVType *BaseType, unsigned NumElements, Register VReg, MachineInstr &I, const SPIRVInstrInfo &TII) { SPIRVType *SpirvType = @@ -43,7 +43,7 @@ SPIRVType *SPIRVGlobalRegistry::assignVectTypeToVReg( return SpirvType; } -SPIRVType *SPIRVGlobalRegistry::assignTypeToVReg( +SPIRVType *SPIRVGlobalTypeRegistry::assignTypeToVReg( const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR) { @@ -53,7 +53,7 @@ SPIRVType *SPIRVGlobalRegistry::assignTypeToVReg( return SpirvType; } -void SPIRVGlobalRegistry::assignSPIRVTypeToVReg(SPIRVType *SpirvType, +void SPIRVGlobalTypeRegistry::assignSPIRVTypeToVReg(SPIRVType *SpirvType, Register VReg, MachineFunction &MF) { VRegToTypeMap[&MF][VReg] = SpirvType; @@ -72,12 +72,12 @@ static Register createTypeVReg(MachineRegisterInfo &MRI) { return Res; } -SPIRVType *SPIRVGlobalRegistry::getOpTypeBool(MachineIRBuilder &MIRBuilder) { +SPIRVType *SPIRVGlobalTypeRegistry::getOpTypeBool(MachineIRBuilder &MIRBuilder) { return MIRBuilder.buildInstr(SPIRV::OpTypeBool) .addDef(createTypeVReg(MIRBuilder)); } -SPIRVType *SPIRVGlobalRegistry::getOpTypeInt(uint32_t Width, +SPIRVType *SPIRVGlobalTypeRegistry::getOpTypeInt(uint32_t Width, MachineIRBuilder &MIRBuilder, bool IsSigned) { assert(Width <= 64 && "Unsupported integer width!"); @@ -97,7 +97,7 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeInt(uint32_t Width, return MIB; } -SPIRVType *SPIRVGlobalRegistry::getOpTypeFloat(uint32_t Width, +SPIRVType *SPIRVGlobalTypeRegistry::getOpTypeFloat(uint32_t Width, MachineIRBuilder &MIRBuilder) { auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeFloat) .addDef(createTypeVReg(MIRBuilder)) @@ -105,12 +105,12 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeFloat(uint32_t Width, return MIB; } -SPIRVType *SPIRVGlobalRegistry::getOpTypeVoid(MachineIRBuilder &MIRBuilder) { +SPIRVType *SPIRVGlobalTypeRegistry::getOpTypeVoid(MachineIRBuilder &MIRBuilder) { return MIRBuilder.buildInstr(SPIRV::OpTypeVoid) .addDef(createTypeVReg(MIRBuilder)); } -SPIRVType *SPIRVGlobalRegistry::getOpTypeVector(uint32_t NumElems, +SPIRVType *SPIRVGlobalTypeRegistry::getOpTypeVector(uint32_t NumElems, SPIRVType *ElemType, MachineIRBuilder &MIRBuilder) { auto EleOpc = ElemType->getOpcode(); @@ -126,7 +126,7 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeVector(uint32_t NumElems, } std::tuple -SPIRVGlobalRegistry::getOrCreateConstIntReg(uint64_t Val, SPIRVType *SpvType, +SPIRVGlobalTypeRegistry::getOrCreateConstIntReg(uint64_t Val, SPIRVType *SpvType, MachineIRBuilder *MIRBuilder, MachineInstr *I, const SPIRVInstrInfo *TII) { @@ -153,7 +153,7 @@ SPIRVGlobalRegistry::getOrCreateConstIntReg(uint64_t Val, SPIRVType *SpvType, return std::make_tuple(Res, CI, NewInstr); } -Register SPIRVGlobalRegistry::getOrCreateConstInt(uint64_t Val, MachineInstr &I, +Register SPIRVGlobalTypeRegistry::getOrCreateConstInt(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII) { assert(SpvType); @@ -184,7 +184,7 @@ Register SPIRVGlobalRegistry::getOrCreateConstInt(uint64_t Val, MachineInstr &I, return Res; } -Register SPIRVGlobalRegistry::buildConstantInt(uint64_t Val, +Register SPIRVGlobalTypeRegistry::buildConstantInt(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType, bool EmitIR) { @@ -230,7 +230,7 @@ Register SPIRVGlobalRegistry::buildConstantInt(uint64_t Val, return Res; } -Register SPIRVGlobalRegistry::buildConstantFP(APFloat Val, +Register SPIRVGlobalTypeRegistry::buildConstantFP(APFloat Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType) { auto &MF = MIRBuilder.getMF(); @@ -254,7 +254,7 @@ Register SPIRVGlobalRegistry::buildConstantFP(APFloat Val, return Res; } -Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull( +Register SPIRVGlobalTypeRegistry::getOrCreateIntCompositeOrNull( uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, Constant *CA, unsigned BitWidth, unsigned ElemCnt) { @@ -297,7 +297,7 @@ Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull( } Register -SPIRVGlobalRegistry::getOrCreateConsIntVector(uint64_t Val, MachineInstr &I, +SPIRVGlobalTypeRegistry::getOrCreateConsIntVector(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII) { const Type *LLVMTy = getTypeForSPIRVType(SpvType); @@ -313,7 +313,7 @@ SPIRVGlobalRegistry::getOrCreateConsIntVector(uint64_t Val, MachineInstr &I, } Register -SPIRVGlobalRegistry::getOrCreateConsIntArray(uint64_t Val, MachineInstr &I, +SPIRVGlobalTypeRegistry::getOrCreateConsIntArray(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII) { const Type *LLVMTy = getTypeForSPIRVType(SpvType); @@ -329,7 +329,7 @@ SPIRVGlobalRegistry::getOrCreateConsIntArray(uint64_t Val, MachineInstr &I, LLVMArrTy->getNumElements()); } -Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull( +Register SPIRVGlobalTypeRegistry::getOrCreateIntCompositeOrNull( uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType, bool EmitIR, Constant *CA, unsigned BitWidth, unsigned ElemCnt) { Register Res = DT.find(CA, CurMF); @@ -366,7 +366,7 @@ Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull( } Register -SPIRVGlobalRegistry::getOrCreateConsIntVector(uint64_t Val, +SPIRVGlobalTypeRegistry::getOrCreateConsIntVector(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType, bool EmitIR) { const Type *LLVMTy = getTypeForSPIRVType(SpvType); @@ -383,7 +383,7 @@ SPIRVGlobalRegistry::getOrCreateConsIntVector(uint64_t Val, } Register -SPIRVGlobalRegistry::getOrCreateConsIntArray(uint64_t Val, +SPIRVGlobalTypeRegistry::getOrCreateConsIntArray(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType, bool EmitIR) { const Type *LLVMTy = getTypeForSPIRVType(SpvType); @@ -401,7 +401,7 @@ SPIRVGlobalRegistry::getOrCreateConsIntArray(uint64_t Val, } Register -SPIRVGlobalRegistry::getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder, +SPIRVGlobalTypeRegistry::getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder, SPIRVType *SpvType) { const Type *LLVMTy = getTypeForSPIRVType(SpvType); const PointerType *LLVMPtrTy = cast(LLVMTy); @@ -420,7 +420,7 @@ SPIRVGlobalRegistry::getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder, return Res; } -Register SPIRVGlobalRegistry::buildConstantSampler( +Register SPIRVGlobalTypeRegistry::buildConstantSampler( Register ResReg, unsigned AddrMode, unsigned Param, unsigned FilerMode, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType) { SPIRVType *SampTy; @@ -443,7 +443,7 @@ Register SPIRVGlobalRegistry::buildConstantSampler( return Res->getOperand(0).getReg(); } -Register SPIRVGlobalRegistry::buildGlobalVariable( +Register SPIRVGlobalTypeRegistry::buildGlobalVariable( Register ResVReg, SPIRVType *BaseType, StringRef Name, const GlobalValue *GV, SPIRV::StorageClass::StorageClass Storage, const MachineInstr *Init, bool IsConst, bool HasLinkageTy, @@ -527,7 +527,7 @@ Register SPIRVGlobalRegistry::buildGlobalVariable( return Reg; } -SPIRVType *SPIRVGlobalRegistry::getOpTypeArray(uint32_t NumElems, +SPIRVType *SPIRVGlobalTypeRegistry::getOpTypeArray(uint32_t NumElems, SPIRVType *ElemType, MachineIRBuilder &MIRBuilder, bool EmitIR) { @@ -542,7 +542,7 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeArray(uint32_t NumElems, return MIB; } -SPIRVType *SPIRVGlobalRegistry::getOpTypeOpaque(const StructType *Ty, +SPIRVType *SPIRVGlobalTypeRegistry::getOpTypeOpaque(const StructType *Ty, MachineIRBuilder &MIRBuilder) { assert(Ty->hasName()); const StringRef Name = Ty->hasName() ? Ty->getName() : ""; @@ -553,7 +553,7 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeOpaque(const StructType *Ty, return MIB; } -SPIRVType *SPIRVGlobalRegistry::getOpTypeStruct(const StructType *Ty, +SPIRVType *SPIRVGlobalTypeRegistry::getOpTypeStruct(const StructType *Ty, MachineIRBuilder &MIRBuilder, bool EmitIR) { SmallVector FieldTypes; @@ -574,7 +574,7 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeStruct(const StructType *Ty, return MIB; } -SPIRVType *SPIRVGlobalRegistry::getOrCreateSpecialType( +SPIRVType *SPIRVGlobalTypeRegistry::getOrCreateSpecialType( const Type *Ty, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AccQual) { // Some OpenCL and SPIRV builtins like image2d_t are passed in as @@ -587,7 +587,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSpecialType( return SPIRV::lowerBuiltinType(Ty, AccQual, MIRBuilder, this); } -SPIRVType *SPIRVGlobalRegistry::getOpTypePointer( +SPIRVType *SPIRVGlobalTypeRegistry::getOpTypePointer( SPIRV::StorageClass::StorageClass SC, SPIRVType *ElemType, MachineIRBuilder &MIRBuilder, Register Reg) { if (!Reg.isValid()) @@ -598,14 +598,14 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypePointer( .addUse(getSPIRVTypeID(ElemType)); } -SPIRVType *SPIRVGlobalRegistry::getOpTypeForwardPointer( +SPIRVType *SPIRVGlobalTypeRegistry::getOpTypeForwardPointer( SPIRV::StorageClass::StorageClass SC, MachineIRBuilder &MIRBuilder) { return MIRBuilder.buildInstr(SPIRV::OpTypeForwardPointer) .addUse(createTypeVReg(MIRBuilder)) .addImm(static_cast(SC)); } -SPIRVType *SPIRVGlobalRegistry::getOpTypeFunction( +SPIRVType *SPIRVGlobalTypeRegistry::getOpTypeFunction( SPIRVType *RetType, const SmallVectorImpl &ArgTypes, MachineIRBuilder &MIRBuilder) { auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeFunction) @@ -616,7 +616,7 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeFunction( return MIB; } -SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeFunctionWithArgs( +SPIRVType *SPIRVGlobalTypeRegistry::getOrCreateOpTypeFunctionWithArgs( const Type *Ty, SPIRVType *RetType, const SmallVectorImpl &ArgTypes, MachineIRBuilder &MIRBuilder) { @@ -627,7 +627,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeFunctionWithArgs( return finishCreatingSPIRVType(Ty, SpirvType); } -SPIRVType *SPIRVGlobalRegistry::findSPIRVType( +SPIRVType *SPIRVGlobalTypeRegistry::findSPIRVType( const Type *Ty, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AccQual, bool EmitIR) { Register Reg = DT.find(Ty, &MIRBuilder.getMF()); @@ -638,14 +638,14 @@ SPIRVType *SPIRVGlobalRegistry::findSPIRVType( return restOfCreateSPIRVType(Ty, MIRBuilder, AccQual, EmitIR); } -Register SPIRVGlobalRegistry::getSPIRVTypeID(const SPIRVType *SpirvType) const { +Register SPIRVGlobalTypeRegistry::getSPIRVTypeID(const SPIRVType *SpirvType) const { assert(SpirvType && "Attempting to get type id for nullptr type."); if (SpirvType->getOpcode() == SPIRV::OpTypeForwardPointer) return SpirvType->uses().begin()->getReg(); return SpirvType->defs().begin()->getReg(); } -SPIRVType *SPIRVGlobalRegistry::createSPIRVType( +SPIRVType *SPIRVGlobalTypeRegistry::createSPIRVType( const Type *Ty, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AccQual, bool EmitIR) { if (isSpecialOpaqueType(Ty)) @@ -720,7 +720,7 @@ SPIRVType *SPIRVGlobalRegistry::createSPIRVType( llvm_unreachable("Unable to convert LLVM type to SPIRVType"); } -SPIRVType *SPIRVGlobalRegistry::restOfCreateSPIRVType( +SPIRVType *SPIRVGlobalTypeRegistry::restOfCreateSPIRVType( const Type *Ty, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR) { if (TypesInProcessing.count(Ty) && !Ty->isPointerTy()) @@ -740,7 +740,7 @@ SPIRVType *SPIRVGlobalRegistry::restOfCreateSPIRVType( return SpirvType; } -SPIRVType *SPIRVGlobalRegistry::getSPIRVTypeForVReg(Register VReg) const { +SPIRVType *SPIRVGlobalTypeRegistry::getSPIRVTypeForVReg(Register VReg) const { auto t = VRegToTypeMap.find(CurMF); if (t != VRegToTypeMap.end()) { auto tt = t->second.find(VReg); @@ -750,7 +750,7 @@ SPIRVType *SPIRVGlobalRegistry::getSPIRVTypeForVReg(Register VReg) const { return nullptr; } -SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVType( +SPIRVType *SPIRVGlobalTypeRegistry::getOrCreateSPIRVType( const Type *Ty, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR) { Register Reg = DT.find(Ty, &MIRBuilder.getMF()); @@ -773,14 +773,14 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVType( return STy; } -bool SPIRVGlobalRegistry::isScalarOfType(Register VReg, +bool SPIRVGlobalTypeRegistry::isScalarOfType(Register VReg, unsigned TypeOpcode) const { SPIRVType *Type = getSPIRVTypeForVReg(VReg); assert(Type && "isScalarOfType VReg has no type assigned"); return Type->getOpcode() == TypeOpcode; } -bool SPIRVGlobalRegistry::isScalarOrVectorOfType(Register VReg, +bool SPIRVGlobalTypeRegistry::isScalarOrVectorOfType(Register VReg, unsigned TypeOpcode) const { SPIRVType *Type = getSPIRVTypeForVReg(VReg); assert(Type && "isScalarOrVectorOfType VReg has no type assigned"); @@ -795,7 +795,7 @@ bool SPIRVGlobalRegistry::isScalarOrVectorOfType(Register VReg, } unsigned -SPIRVGlobalRegistry::getScalarOrVectorBitWidth(const SPIRVType *Type) const { +SPIRVGlobalTypeRegistry::getScalarOrVectorBitWidth(const SPIRVType *Type) const { assert(Type && "Invalid Type pointer"); if (Type->getOpcode() == SPIRV::OpTypeVector) { auto EleTypeReg = Type->getOperand(1).getReg(); @@ -809,7 +809,7 @@ SPIRVGlobalRegistry::getScalarOrVectorBitWidth(const SPIRVType *Type) const { llvm_unreachable("Attempting to get bit width of non-integer/float type."); } -bool SPIRVGlobalRegistry::isScalarOrVectorSigned(const SPIRVType *Type) const { +bool SPIRVGlobalTypeRegistry::isScalarOrVectorSigned(const SPIRVType *Type) const { assert(Type && "Invalid Type pointer"); if (Type->getOpcode() == SPIRV::OpTypeVector) { auto EleTypeReg = Type->getOperand(1).getReg(); @@ -821,7 +821,7 @@ bool SPIRVGlobalRegistry::isScalarOrVectorSigned(const SPIRVType *Type) const { } SPIRV::StorageClass::StorageClass -SPIRVGlobalRegistry::getPointerStorageClass(Register VReg) const { +SPIRVGlobalTypeRegistry::getPointerStorageClass(Register VReg) const { SPIRVType *Type = getSPIRVTypeForVReg(VReg); assert(Type && Type->getOpcode() == SPIRV::OpTypePointer && Type->getOperand(1).isImm() && "Pointer type is expected"); @@ -829,7 +829,7 @@ SPIRVGlobalRegistry::getPointerStorageClass(Register VReg) const { Type->getOperand(1).getImm()); } -SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeImage( +SPIRVType *SPIRVGlobalTypeRegistry::getOrCreateOpTypeImage( MachineIRBuilder &MIRBuilder, SPIRVType *SampledType, SPIRV::Dim::Dim Dim, uint32_t Depth, uint32_t Arrayed, uint32_t Multisampled, uint32_t Sampled, SPIRV::ImageFormat::ImageFormat ImageFormat, @@ -854,7 +854,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeImage( } SPIRVType * -SPIRVGlobalRegistry::getOrCreateOpTypeSampler(MachineIRBuilder &MIRBuilder) { +SPIRVGlobalTypeRegistry::getOrCreateOpTypeSampler(MachineIRBuilder &MIRBuilder) { SPIRV::SamplerTypeDescriptor TD; if (auto *Res = checkSpecialInstr(TD, MIRBuilder)) return Res; @@ -863,7 +863,7 @@ SPIRVGlobalRegistry::getOrCreateOpTypeSampler(MachineIRBuilder &MIRBuilder) { return MIRBuilder.buildInstr(SPIRV::OpTypeSampler).addDef(ResVReg); } -SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypePipe( +SPIRVType *SPIRVGlobalTypeRegistry::getOrCreateOpTypePipe( MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AccessQual) { SPIRV::PipeTypeDescriptor TD(AccessQual); @@ -876,7 +876,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypePipe( .addImm(AccessQual); } -SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeDeviceEvent( +SPIRVType *SPIRVGlobalTypeRegistry::getOrCreateOpTypeDeviceEvent( MachineIRBuilder &MIRBuilder) { SPIRV::DeviceEventTypeDescriptor TD; if (auto *Res = checkSpecialInstr(TD, MIRBuilder)) @@ -886,7 +886,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeDeviceEvent( return MIRBuilder.buildInstr(SPIRV::OpTypeDeviceEvent).addDef(ResVReg); } -SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeSampledImage( +SPIRVType *SPIRVGlobalTypeRegistry::getOrCreateOpTypeSampledImage( SPIRVType *ImageType, MachineIRBuilder &MIRBuilder) { SPIRV::SampledImageTypeDescriptor TD( SPIRVToLLVMType.lookup(MIRBuilder.getMF().getRegInfo().getVRegDef( @@ -901,7 +901,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeSampledImage( .addUse(getSPIRVTypeID(ImageType)); } -SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeByOpcode( +SPIRVType *SPIRVGlobalTypeRegistry::getOrCreateOpTypeByOpcode( const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode) { Register ResVReg = DT.find(Ty, &MIRBuilder.getMF()); if (ResVReg.isValid()) @@ -912,7 +912,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeByOpcode( } const MachineInstr * -SPIRVGlobalRegistry::checkSpecialInstr(const SPIRV::SpecialTypeDescriptor &TD, +SPIRVGlobalTypeRegistry::checkSpecialInstr(const SPIRV::SpecialTypeDescriptor &TD, MachineIRBuilder &MIRBuilder) { Register Reg = DT.find(TD, &MIRBuilder.getMF()); if (Reg.isValid()) @@ -922,7 +922,7 @@ SPIRVGlobalRegistry::checkSpecialInstr(const SPIRV::SpecialTypeDescriptor &TD, // TODO: maybe use tablegen to implement this. SPIRVType * -SPIRVGlobalRegistry::getOrCreateSPIRVTypeByName(StringRef TypeStr, +SPIRVGlobalTypeRegistry::getOrCreateSPIRVTypeByName(StringRef TypeStr, MachineIRBuilder &MIRBuilder) { unsigned VecElts = 0; auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); @@ -959,14 +959,14 @@ SPIRVGlobalRegistry::getOrCreateSPIRVTypeByName(StringRef TypeStr, } SPIRVType * -SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType(unsigned BitWidth, +SPIRVGlobalTypeRegistry::getOrCreateSPIRVIntegerType(unsigned BitWidth, MachineIRBuilder &MIRBuilder) { return getOrCreateSPIRVType( IntegerType::get(MIRBuilder.getMF().getFunction().getContext(), BitWidth), MIRBuilder); } -SPIRVType *SPIRVGlobalRegistry::finishCreatingSPIRVType(const Type *LLVMTy, +SPIRVType *SPIRVGlobalTypeRegistry::finishCreatingSPIRVType(const Type *LLVMTy, SPIRVType *SpirvType) { assert(CurMF == SpirvType->getMF()); VRegToTypeMap[CurMF][getSPIRVTypeID(SpirvType)] = SpirvType; @@ -975,7 +975,7 @@ SPIRVType *SPIRVGlobalRegistry::finishCreatingSPIRVType(const Type *LLVMTy, return SpirvType; } -SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType( +SPIRVType *SPIRVGlobalTypeRegistry::getOrCreateSPIRVIntegerType( unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII) { Type *LLVMTy = IntegerType::get(CurMF->getFunction().getContext(), BitWidth); Register Reg = DT.find(LLVMTy, CurMF); @@ -990,14 +990,14 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType( } SPIRVType * -SPIRVGlobalRegistry::getOrCreateSPIRVBoolType(MachineIRBuilder &MIRBuilder) { +SPIRVGlobalTypeRegistry::getOrCreateSPIRVBoolType(MachineIRBuilder &MIRBuilder) { return getOrCreateSPIRVType( IntegerType::get(MIRBuilder.getMF().getFunction().getContext(), 1), MIRBuilder); } SPIRVType * -SPIRVGlobalRegistry::getOrCreateSPIRVBoolType(MachineInstr &I, +SPIRVGlobalTypeRegistry::getOrCreateSPIRVBoolType(MachineInstr &I, const SPIRVInstrInfo &TII) { Type *LLVMTy = IntegerType::get(CurMF->getFunction().getContext(), 1); Register Reg = DT.find(LLVMTy, CurMF); @@ -1009,7 +1009,7 @@ SPIRVGlobalRegistry::getOrCreateSPIRVBoolType(MachineInstr &I, return finishCreatingSPIRVType(LLVMTy, MIB); } -SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVVectorType( +SPIRVType *SPIRVGlobalTypeRegistry::getOrCreateSPIRVVectorType( SPIRVType *BaseType, unsigned NumElements, MachineIRBuilder &MIRBuilder) { return getOrCreateSPIRVType( FixedVectorType::get(const_cast(getTypeForSPIRVType(BaseType)), @@ -1017,7 +1017,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVVectorType( MIRBuilder); } -SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVVectorType( +SPIRVType *SPIRVGlobalTypeRegistry::getOrCreateSPIRVVectorType( SPIRVType *BaseType, unsigned NumElements, MachineInstr &I, const SPIRVInstrInfo &TII) { Type *LLVMTy = FixedVectorType::get( @@ -1033,7 +1033,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVVectorType( return finishCreatingSPIRVType(LLVMTy, MIB); } -SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVArrayType( +SPIRVType *SPIRVGlobalTypeRegistry::getOrCreateSPIRVArrayType( SPIRVType *BaseType, unsigned NumElements, MachineInstr &I, const SPIRVInstrInfo &TII) { Type *LLVMTy = ArrayType::get( @@ -1051,7 +1051,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVArrayType( return finishCreatingSPIRVType(LLVMTy, MIB); } -SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVPointerType( +SPIRVType *SPIRVGlobalTypeRegistry::getOrCreateSPIRVPointerType( SPIRVType *BaseType, MachineIRBuilder &MIRBuilder, SPIRV::StorageClass::StorageClass SClass) { return getOrCreateSPIRVType( @@ -1060,7 +1060,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVPointerType( MIRBuilder); } -SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVPointerType( +SPIRVType *SPIRVGlobalTypeRegistry::getOrCreateSPIRVPointerType( SPIRVType *BaseType, MachineInstr &I, const SPIRVInstrInfo &TII, SPIRV::StorageClass::StorageClass SC) { Type *LLVMTy = @@ -1077,7 +1077,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVPointerType( return finishCreatingSPIRVType(LLVMTy, MIB); } -Register SPIRVGlobalRegistry::getOrCreateUndef(MachineInstr &I, +Register SPIRVGlobalTypeRegistry::getOrCreateUndef(MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII) { assert(SpvType); diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h b/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.h similarity index 97% rename from llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h rename to llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.h index 88769f84b3e5..61564e474ba2 100644 --- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h +++ b/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.h @@ -1,4 +1,4 @@ -//===-- SPIRVGlobalRegistry.h - SPIR-V Global Registry ----------*- C++ -*-===// +//===-- SPIRVGlobalTypeRegistry.h - SPIR-V Global Registry ----------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,15 +6,15 @@ // //===----------------------------------------------------------------------===// // -// SPIRVGlobalRegistry is used to maintain rich type information required for +// SPIRVGlobalTypeRegistry is used to maintain rich type information required for // SPIR-V even after lowering from LLVM IR to GMIR. It can convert an llvm::Type // into an OpTypeXXX instruction, and map it to a virtual register. Also it // builds and supports consistency of constants and global variables. // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVTYPEMANAGER_H -#define LLVM_LIB_TARGET_SPIRV_SPIRVTYPEMANAGER_H +#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVGLOBALTYPEREGISTRY_H +#define LLVM_LIB_TARGET_SPIRV_SPIRVGLOBALTYPEREGISTRY_H #include "MCTargetDesc/SPIRVBaseInfo.h" #include "SPIRVDuplicatesTracker.h" @@ -24,7 +24,7 @@ namespace llvm { using SPIRVType = const MachineInstr; -class SPIRVGlobalRegistry { +class SPIRVGlobalTypeRegistry { // Registers holding values which have types associated with them. // Initialized upon VReg definition in IRTranslator. // Do not confuse this with DuplicatesTracker as DT maps Type* to @@ -64,7 +64,7 @@ class SPIRVGlobalRegistry { bool EmitIR); public: - SPIRVGlobalRegistry(unsigned PointerSize); + SPIRVGlobalTypeRegistry(unsigned PointerSize); MachineFunction *CurMF; @@ -312,4 +312,4 @@ class SPIRVGlobalRegistry { unsigned Opcode); }; } // end namespace llvm -#endif // LLLVM_LIB_TARGET_SPIRV_SPIRVTYPEMANAGER_H +#endif // LLVM_LIB_TARGET_SPIRV_SPIRVGLOBALTYPEREGISTRY_H diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp index c11b36a08854..50b39bb9df58 100644 --- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp @@ -274,16 +274,16 @@ lookupBuiltin(StringRef DemangledCall, /// \returns Tuple of the resulting register and its type. static std::tuple buildBoolRegister(MachineIRBuilder &MIRBuilder, const SPIRVType *ResultType, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { LLT Type; - SPIRVType *BoolType = GR->getOrCreateSPIRVBoolType(MIRBuilder); + SPIRVType *BoolType = GTR->getOrCreateSPIRVBoolType(MIRBuilder); if (ResultType->getOpcode() == SPIRV::OpTypeVector) { unsigned VectorElements = ResultType->getOperand(2).getImm(); BoolType = - GR->getOrCreateSPIRVVectorType(BoolType, VectorElements, MIRBuilder); + GTR->getOrCreateSPIRVVectorType(BoolType, VectorElements, MIRBuilder); const FixedVectorType *LLVMVectorType = - cast(GR->getTypeForSPIRVType(BoolType)); + cast(GTR->getTypeForSPIRVType(BoolType)); Type = LLT::vector(LLVMVectorType->getElementCount(), 1); } else { Type = LLT::scalar(1); @@ -291,7 +291,7 @@ buildBoolRegister(MachineIRBuilder &MIRBuilder, const SPIRVType *ResultType, Register ResultRegister = MIRBuilder.getMRI()->createGenericVirtualRegister(Type); - GR->assignSPIRVTypeToVReg(BoolType, ResultRegister, MIRBuilder.getMF()); + GTR->assignSPIRVTypeToVReg(BoolType, ResultRegister, MIRBuilder.getMF()); return std::make_tuple(ResultRegister, BoolType); } @@ -300,17 +300,17 @@ buildBoolRegister(MachineIRBuilder &MIRBuilder, const SPIRVType *ResultType, static bool buildSelectInst(MachineIRBuilder &MIRBuilder, Register ReturnRegister, Register SourceRegister, const SPIRVType *ReturnType, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { Register TrueConst, FalseConst; if (ReturnType->getOpcode() == SPIRV::OpTypeVector) { - unsigned Bits = GR->getScalarOrVectorBitWidth(ReturnType); + unsigned Bits = GTR->getScalarOrVectorBitWidth(ReturnType); uint64_t AllOnes = APInt::getAllOnes(Bits).getZExtValue(); - TrueConst = GR->getOrCreateConsIntVector(AllOnes, MIRBuilder, ReturnType); - FalseConst = GR->getOrCreateConsIntVector(0, MIRBuilder, ReturnType); + TrueConst = GTR->getOrCreateConsIntVector(AllOnes, MIRBuilder, ReturnType); + FalseConst = GTR->getOrCreateConsIntVector(0, MIRBuilder, ReturnType); } else { - TrueConst = GR->buildConstantInt(1, MIRBuilder, ReturnType); - FalseConst = GR->buildConstantInt(0, MIRBuilder, ReturnType); + TrueConst = GTR->buildConstantInt(1, MIRBuilder, ReturnType); + FalseConst = GTR->buildConstantInt(0, MIRBuilder, ReturnType); } return MIRBuilder.buildSelect(ReturnRegister, SourceRegister, TrueConst, FalseConst); @@ -320,13 +320,13 @@ static bool buildSelectInst(MachineIRBuilder &MIRBuilder, /// \p DestinationReg. static Register buildLoadInst(SPIRVType *BaseType, Register PtrRegister, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR, LLT LowLevelType, + SPIRVGlobalTypeRegistry *GTR, LLT LowLevelType, Register DestinationReg = Register(0)) { MachineRegisterInfo *MRI = MIRBuilder.getMRI(); if (!DestinationReg.isValid()) { DestinationReg = MRI->createVirtualRegister(&SPIRV::IDRegClass); MRI->setType(DestinationReg, LLT::scalar(32)); - GR->assignSPIRVTypeToVReg(BaseType, DestinationReg, MIRBuilder.getMF()); + GTR->assignSPIRVTypeToVReg(BaseType, DestinationReg, MIRBuilder.getMF()); } // TODO: consider using correct address space and alignment (p0 is canonical // type for selection though). @@ -339,27 +339,27 @@ static Register buildLoadInst(SPIRVType *BaseType, Register PtrRegister, /// variable of \p BuiltinValue value. static Register buildBuiltinVariableLoad(MachineIRBuilder &MIRBuilder, SPIRVType *VariableType, - SPIRVGlobalRegistry *GR, + SPIRVGlobalTypeRegistry *GTR, SPIRV::BuiltIn::BuiltIn BuiltinValue, LLT LLType, Register Reg = Register(0)) { Register NewRegister = MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass); MIRBuilder.getMRI()->setType(NewRegister, - LLT::pointer(0, GR->getPointerSize())); - SPIRVType *PtrType = GR->getOrCreateSPIRVPointerType( + LLT::pointer(0, GTR->getPointerSize())); + SPIRVType *PtrType = GTR->getOrCreateSPIRVPointerType( VariableType, MIRBuilder, SPIRV::StorageClass::Input); - GR->assignSPIRVTypeToVReg(PtrType, NewRegister, MIRBuilder.getMF()); + GTR->assignSPIRVTypeToVReg(PtrType, NewRegister, MIRBuilder.getMF()); // Set up the global OpVariable with the necessary builtin decorations. - Register Variable = GR->buildGlobalVariable( + Register Variable = GTR->buildGlobalVariable( NewRegister, PtrType, getLinkStringForBuiltIn(BuiltinValue), nullptr, SPIRV::StorageClass::Input, nullptr, true, true, SPIRV::LinkageType::Import, MIRBuilder, false); // Load the value from the global variable. Register LoadedRegister = - buildLoadInst(VariableType, Variable, MIRBuilder, GR, LLType, Reg); + buildLoadInst(VariableType, Variable, MIRBuilder, GTR, LLType, Reg); MIRBuilder.getMRI()->setType(LoadedRegister, LLType); return LoadedRegister; } @@ -370,7 +370,7 @@ static Register buildBuiltinVariableLoad(MachineIRBuilder &MIRBuilder, /// SPIRVType in ASSIGN_TYPE, otherwise create it from \p Ty. Defined in /// SPIRVPreLegalizer.cpp. extern Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy, - SPIRVGlobalRegistry *GR, + SPIRVGlobalTypeRegistry *GTR, MachineIRBuilder &MIB, MachineRegisterInfo &MRI); @@ -410,15 +410,15 @@ static SPIRV::Scope::Scope getSPIRVScope(SPIRV::CLMemoryScope ClScope) { } static Register buildConstantIntReg(uint64_t Val, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR, + SPIRVGlobalTypeRegistry *GTR, unsigned BitWidth = 32) { - SPIRVType *IntType = GR->getOrCreateSPIRVIntegerType(BitWidth, MIRBuilder); - return GR->buildConstantInt(Val, MIRBuilder, IntType); + SPIRVType *IntType = GTR->getOrCreateSPIRVIntegerType(BitWidth, MIRBuilder); + return GTR->buildConstantInt(Val, MIRBuilder, IntType); } static Register buildScopeReg(Register CLScopeRegister, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR, + SPIRVGlobalTypeRegistry *GTR, const MachineRegisterInfo *MRI) { auto CLScope = static_cast(getIConstVal(CLScopeRegister, MRI)); @@ -427,18 +427,18 @@ static Register buildScopeReg(Register CLScopeRegister, if (CLScope == static_cast(Scope)) return CLScopeRegister; - return buildConstantIntReg(Scope, MIRBuilder, GR); + return buildConstantIntReg(Scope, MIRBuilder, GTR); } static Register buildMemSemanticsReg(Register SemanticsRegister, Register PtrRegister, const MachineRegisterInfo *MRI, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { std::memory_order Order = static_cast(getIConstVal(SemanticsRegister, MRI)); unsigned Semantics = getSPIRVMemSemantics(Order) | - getMemSemanticsForStorageClass(GR->getPointerStorageClass(PtrRegister)); + getMemSemanticsForStorageClass(GTR->getPointerStorageClass(PtrRegister)); if (Order == Semantics) return SemanticsRegister; @@ -461,7 +461,7 @@ static bool buildAtomicInitInst(const SPIRV::IncomingCall *Call, /// Helper function for building an atomic load instruction. static bool buildAtomicLoadInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { Register PtrRegister = Call->Arguments[0]; // TODO: if true insert call to __translate_ocl_memory_sccope before // OpAtomicLoad and the function implementation. We can use Translator's @@ -470,22 +470,22 @@ static bool buildAtomicLoadInst(const SPIRV::IncomingCall *Call, if (Call->Arguments.size() > 1) ScopeRegister = Call->Arguments[1]; else - ScopeRegister = buildConstantIntReg(SPIRV::Scope::Device, MIRBuilder, GR); + ScopeRegister = buildConstantIntReg(SPIRV::Scope::Device, MIRBuilder, GTR); Register MemSemanticsReg; if (Call->Arguments.size() > 2) { // TODO: Insert call to __translate_ocl_memory_order before OpAtomicLoad. MemSemanticsReg = Call->Arguments[2]; } else { - int Semantics = - SPIRV::MemorySemantics::SequentiallyConsistent | - getMemSemanticsForStorageClass(GR->getPointerStorageClass(PtrRegister)); - MemSemanticsReg = buildConstantIntReg(Semantics, MIRBuilder, GR); + int Semantics = SPIRV::MemorySemantics::SequentiallyConsistent | + getMemSemanticsForStorageClass( + GTR->getPointerStorageClass(PtrRegister)); + MemSemanticsReg = buildConstantIntReg(Semantics, MIRBuilder, GTR); } MIRBuilder.buildInstr(SPIRV::OpAtomicLoad) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)) + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)) .addUse(PtrRegister) .addUse(ScopeRegister) .addUse(MemSemanticsReg); @@ -495,14 +495,14 @@ static bool buildAtomicLoadInst(const SPIRV::IncomingCall *Call, /// Helper function for building an atomic store instruction. static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { Register ScopeRegister = - buildConstantIntReg(SPIRV::Scope::Device, MIRBuilder, GR); + buildConstantIntReg(SPIRV::Scope::Device, MIRBuilder, GTR); Register PtrRegister = Call->Arguments[0]; int Semantics = SPIRV::MemorySemantics::SequentiallyConsistent | - getMemSemanticsForStorageClass(GR->getPointerStorageClass(PtrRegister)); - Register MemSemanticsReg = buildConstantIntReg(Semantics, MIRBuilder, GR); + getMemSemanticsForStorageClass(GTR->getPointerStorageClass(PtrRegister)); + Register MemSemanticsReg = buildConstantIntReg(Semantics, MIRBuilder, GTR); MIRBuilder.buildInstr(SPIRV::OpAtomicStore) .addUse(PtrRegister) @@ -515,7 +515,7 @@ static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call, /// Helper function for building an atomic compare-exchange instruction. static bool buildAtomicCompareExchangeInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; unsigned Opcode = SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode; @@ -525,17 +525,17 @@ static bool buildAtomicCompareExchangeInst(const SPIRV::IncomingCall *Call, Register ObjectPtr = Call->Arguments[0]; // Pointer (volatile A *object.) Register ExpectedArg = Call->Arguments[1]; // Comparator (C* expected). Register Desired = Call->Arguments[2]; // Value (C Desired). - SPIRVType *SpvDesiredTy = GR->getSPIRVTypeForVReg(Desired); + SPIRVType *SpvDesiredTy = GTR->getSPIRVTypeForVReg(Desired); LLT DesiredLLT = MRI->getType(Desired); - assert(GR->getSPIRVTypeForVReg(ObjectPtr)->getOpcode() == + assert(GTR->getSPIRVTypeForVReg(ObjectPtr)->getOpcode() == SPIRV::OpTypePointer); - unsigned ExpectedType = GR->getSPIRVTypeForVReg(ExpectedArg)->getOpcode(); + unsigned ExpectedType = GTR->getSPIRVTypeForVReg(ExpectedArg)->getOpcode(); assert(IsCmpxchg ? ExpectedType == SPIRV::OpTypeInt : ExpectedType == SPIRV::OpTypePointer); - assert(GR->isScalarOfType(Desired, SPIRV::OpTypeInt)); + assert(GTR->isScalarOfType(Desired, SPIRV::OpTypeInt)); - SPIRVType *SpvObjectPtrTy = GR->getSPIRVTypeForVReg(ObjectPtr); + SPIRVType *SpvObjectPtrTy = GTR->getSPIRVTypeForVReg(ObjectPtr); assert(SpvObjectPtrTy->getOperand(2).isReg() && "SPIRV type is expected"); auto StorageClass = static_cast( SpvObjectPtrTy->getOperand(1).getImm()); @@ -566,9 +566,9 @@ static bool buildAtomicCompareExchangeInst(const SPIRV::IncomingCall *Call, MemSemUnequalReg = Call->Arguments[4]; } if (!MemSemEqualReg.isValid()) - MemSemEqualReg = buildConstantIntReg(MemSemEqual, MIRBuilder, GR); + MemSemEqualReg = buildConstantIntReg(MemSemEqual, MIRBuilder, GTR); if (!MemSemUnequalReg.isValid()) - MemSemUnequalReg = buildConstantIntReg(MemSemUnequal, MIRBuilder, GR); + MemSemUnequalReg = buildConstantIntReg(MemSemUnequal, MIRBuilder, GTR); Register ScopeReg; auto Scope = IsCmpxchg ? SPIRV::Scope::Workgroup : SPIRV::Scope::Device; @@ -582,21 +582,21 @@ static bool buildAtomicCompareExchangeInst(const SPIRV::IncomingCall *Call, ScopeReg = Call->Arguments[5]; } if (!ScopeReg.isValid()) - ScopeReg = buildConstantIntReg(Scope, MIRBuilder, GR); + ScopeReg = buildConstantIntReg(Scope, MIRBuilder, GTR); Register Expected = IsCmpxchg ? ExpectedArg : buildLoadInst(SpvDesiredTy, ExpectedArg, MIRBuilder, - GR, LLT::scalar(32)); + GTR, LLT::scalar(32)); MRI->setType(Expected, DesiredLLT); Register Tmp = !IsCmpxchg ? MRI->createGenericVirtualRegister(DesiredLLT) : Call->ReturnRegister; - GR->assignSPIRVTypeToVReg(SpvDesiredTy, Tmp, MIRBuilder.getMF()); + GTR->assignSPIRVTypeToVReg(SpvDesiredTy, Tmp, MIRBuilder.getMF()); - SPIRVType *IntTy = GR->getOrCreateSPIRVIntegerType(32, MIRBuilder); + SPIRVType *IntTy = GTR->getOrCreateSPIRVIntegerType(32, MIRBuilder); MIRBuilder.buildInstr(Opcode) .addDef(Tmp) - .addUse(GR->getSPIRVTypeID(IntTy)) + .addUse(GTR->getSPIRVTypeID(IntTy)) .addUse(ObjectPtr) .addUse(ScopeReg) .addUse(MemSemEqualReg) @@ -613,7 +613,7 @@ static bool buildAtomicCompareExchangeInst(const SPIRV::IncomingCall *Call, /// Helper function for building an atomic load instruction. static bool buildAtomicRMWInst(const SPIRV::IncomingCall *Call, unsigned Opcode, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { const MachineRegisterInfo *MRI = MIRBuilder.getMRI(); SPIRV::Scope::Scope Scope = SPIRV::Scope::Workgroup; Register ScopeRegister; @@ -621,11 +621,11 @@ static bool buildAtomicRMWInst(const SPIRV::IncomingCall *Call, unsigned Opcode, if (Call->Arguments.size() >= 4) { assert(Call->Arguments.size() == 4 && "Too many args for explicit atomic RMW"); - ScopeRegister = buildScopeReg(Call->Arguments[3], MIRBuilder, GR, MRI); + ScopeRegister = buildScopeReg(Call->Arguments[3], MIRBuilder, GTR, MRI); } if (!ScopeRegister.isValid()) - ScopeRegister = buildConstantIntReg(Scope, MIRBuilder, GR); + ScopeRegister = buildConstantIntReg(Scope, MIRBuilder, GTR); Register PtrRegister = Call->Arguments[0]; unsigned Semantics = SPIRV::MemorySemantics::None; @@ -633,14 +633,14 @@ static bool buildAtomicRMWInst(const SPIRV::IncomingCall *Call, unsigned Opcode, if (Call->Arguments.size() >= 3) MemSemanticsReg = - buildMemSemanticsReg(Call->Arguments[2], PtrRegister, MRI, GR); + buildMemSemanticsReg(Call->Arguments[2], PtrRegister, MRI, GTR); if (!MemSemanticsReg.isValid()) - MemSemanticsReg = buildConstantIntReg(Semantics, MIRBuilder, GR); + MemSemanticsReg = buildConstantIntReg(Semantics, MIRBuilder, GTR); MIRBuilder.buildInstr(Opcode) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)) + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)) .addUse(PtrRegister) .addUse(ScopeRegister) .addUse(MemSemanticsReg) @@ -652,7 +652,7 @@ static bool buildAtomicRMWInst(const SPIRV::IncomingCall *Call, unsigned Opcode, /// OpAtomicFlagTestAndSet). static bool buildAtomicFlagInst(const SPIRV::IncomingCall *Call, unsigned Opcode, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { const MachineRegisterInfo *MRI = MIRBuilder.getMRI(); Register PtrRegister = Call->Arguments[0]; @@ -661,10 +661,10 @@ static bool buildAtomicFlagInst(const SPIRV::IncomingCall *Call, if (Call->Arguments.size() >= 2) MemSemanticsReg = - buildMemSemanticsReg(Call->Arguments[1], PtrRegister, MRI, GR); + buildMemSemanticsReg(Call->Arguments[1], PtrRegister, MRI, GTR); if (!MemSemanticsReg.isValid()) - MemSemanticsReg = buildConstantIntReg(Semantics, MIRBuilder, GR); + MemSemanticsReg = buildConstantIntReg(Semantics, MIRBuilder, GTR); assert((Opcode != SPIRV::OpAtomicFlagClear || (Semantics != SPIRV::MemorySemantics::Acquire && @@ -675,15 +675,15 @@ static bool buildAtomicFlagInst(const SPIRV::IncomingCall *Call, Register ScopeRegister; if (Call->Arguments.size() >= 3) - ScopeRegister = buildScopeReg(Call->Arguments[2], MIRBuilder, GR, MRI); + ScopeRegister = buildScopeReg(Call->Arguments[2], MIRBuilder, GTR, MRI); if (!ScopeRegister.isValid()) - ScopeRegister = buildConstantIntReg(Scope, MIRBuilder, GR); + ScopeRegister = buildConstantIntReg(Scope, MIRBuilder, GTR); auto MIB = MIRBuilder.buildInstr(Opcode); if (Opcode == SPIRV::OpAtomicFlagTestAndSet) MIB.addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)); + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)); MIB.addUse(PtrRegister).addUse(ScopeRegister).addUse(MemSemanticsReg); return true; @@ -693,7 +693,7 @@ static bool buildAtomicFlagInst(const SPIRV::IncomingCall *Call, /// operations. static bool buildBarrierInst(const SPIRV::IncomingCall *Call, unsigned Opcode, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { const MachineRegisterInfo *MRI = MIRBuilder.getMRI(); unsigned MemFlags = getIConstVal(Call->Arguments[0], MRI); unsigned MemSemantics = SPIRV::MemorySemantics::None; @@ -719,7 +719,7 @@ static bool buildBarrierInst(const SPIRV::IncomingCall *Call, unsigned Opcode, if (MemFlags == MemSemantics) MemSemanticsReg = Call->Arguments[0]; else - MemSemanticsReg = buildConstantIntReg(MemSemantics, MIRBuilder, GR); + MemSemanticsReg = buildConstantIntReg(MemSemantics, MIRBuilder, GTR); Register ScopeReg; SPIRV::Scope::Scope Scope = SPIRV::Scope::Workgroup; @@ -743,11 +743,11 @@ static bool buildBarrierInst(const SPIRV::IncomingCall *Call, unsigned Opcode, } if (!ScopeReg.isValid()) - ScopeReg = buildConstantIntReg(Scope, MIRBuilder, GR); + ScopeReg = buildConstantIntReg(Scope, MIRBuilder, GTR); auto MIB = MIRBuilder.buildInstr(Opcode).addUse(ScopeReg); if (Opcode != SPIRV::OpMemoryBarrier) - MIB.addUse(buildConstantIntReg(MemScope, MIRBuilder, GR)); + MIB.addUse(buildConstantIntReg(MemScope, MIRBuilder, GTR)); MIB.addUse(MemSemanticsReg); return true; } @@ -783,7 +783,7 @@ static unsigned getNumSizeComponents(SPIRVType *imgType) { static bool generateExtInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { // Lookup the extended instruction number in the TableGen records. const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; uint32_t Number = @@ -793,7 +793,7 @@ static bool generateExtInst(const SPIRV::IncomingCall *Call, auto MIB = MIRBuilder.buildInstr(SPIRV::OpExtInst) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)) + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)) .addImm(static_cast(SPIRV::InstructionSet::OpenCL_std)) .addImm(Number); @@ -804,7 +804,7 @@ static bool generateExtInst(const SPIRV::IncomingCall *Call, static bool generateRelationalInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { // Lookup the instruction opcode in the TableGen records. const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; unsigned Opcode = @@ -813,24 +813,24 @@ static bool generateRelationalInst(const SPIRV::IncomingCall *Call, Register CompareRegister; SPIRVType *RelationType; std::tie(CompareRegister, RelationType) = - buildBoolRegister(MIRBuilder, Call->ReturnType, GR); + buildBoolRegister(MIRBuilder, Call->ReturnType, GTR); // Build relational instruction. auto MIB = MIRBuilder.buildInstr(Opcode) .addDef(CompareRegister) - .addUse(GR->getSPIRVTypeID(RelationType)); + .addUse(GTR->getSPIRVTypeID(RelationType)); for (auto Argument : Call->Arguments) MIB.addUse(Argument); // Build select instruction. return buildSelectInst(MIRBuilder, Call->ReturnRegister, CompareRegister, - Call->ReturnType, GR); + Call->ReturnType, GTR); } static bool generateGroupInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; const SPIRV::GroupBuiltin *GroupBuiltin = SPIRV::lookupGroupBuiltin(Builtin->Name); @@ -842,10 +842,10 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call, // TODO: support non-constant bool values. assert(ArgInstruction->getOpcode() == TargetOpcode::G_CONSTANT && "Only constant bool value args are supported"); - if (GR->getSPIRVTypeForVReg(Call->Arguments[0])->getOpcode() != + if (GTR->getSPIRVTypeForVReg(Call->Arguments[0])->getOpcode() != SPIRV::OpTypeBool) - Arg0 = GR->buildConstantInt(getIConstVal(ConstRegister, MRI), MIRBuilder, - GR->getOrCreateSPIRVBoolType(MIRBuilder)); + Arg0 = GTR->buildConstantInt(getIConstVal(ConstRegister, MRI), MIRBuilder, + GTR->getOrCreateSPIRVBoolType(MIRBuilder)); } Register GroupResultRegister = Call->ReturnRegister; @@ -860,16 +860,16 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call, if (HasBoolReturnTy) std::tie(GroupResultRegister, GroupResultType) = - buildBoolRegister(MIRBuilder, Call->ReturnType, GR); + buildBoolRegister(MIRBuilder, Call->ReturnType, GTR); auto Scope = Builtin->Name.startswith("sub_group") ? SPIRV::Scope::Subgroup : SPIRV::Scope::Workgroup; - Register ScopeRegister = buildConstantIntReg(Scope, MIRBuilder, GR); + Register ScopeRegister = buildConstantIntReg(Scope, MIRBuilder, GTR); // Build work/sub group instruction. auto MIB = MIRBuilder.buildInstr(GroupBuiltin->Opcode) .addDef(GroupResultRegister) - .addUse(GR->getSPIRVTypeID(GroupResultType)) + .addUse(GTR->getSPIRVTypeID(GroupResultType)) .addUse(ScopeRegister); if (!GroupBuiltin->NoGroupOperation) @@ -883,7 +883,7 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call, // Build select instruction. if (HasBoolReturnTy) buildSelectInst(MIRBuilder, Call->ReturnRegister, GroupResultRegister, - Call->ReturnType, GR); + Call->ReturnType, GTR); return true; } @@ -915,14 +915,14 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call, // extend or truncate. static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR, + SPIRVGlobalTypeRegistry *GTR, SPIRV::BuiltIn::BuiltIn BuiltinValue, uint64_t DefaultValue) { Register IndexRegister = Call->Arguments[0]; const unsigned ResultWidth = Call->ReturnType->getOperand(1).getImm(); - const unsigned PointerSize = GR->getPointerSize(); + const unsigned PointerSize = GTR->getPointerSize(); const SPIRVType *PointerSizeType = - GR->getOrCreateSPIRVIntegerType(PointerSize, MIRBuilder); + GTR->getOrCreateSPIRVIntegerType(PointerSize, MIRBuilder); MachineRegisterInfo *MRI = MIRBuilder.getMRI(); auto IndexInstruction = getDefInstrMaybeConstant(IndexRegister, MRI); @@ -939,24 +939,25 @@ static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call, Register defaultReg = Call->ReturnRegister; if (PointerSize != ResultWidth) { defaultReg = MRI->createGenericVirtualRegister(LLT::scalar(PointerSize)); - GR->assignSPIRVTypeToVReg(PointerSizeType, defaultReg, - MIRBuilder.getMF()); + GTR->assignSPIRVTypeToVReg(PointerSizeType, defaultReg, + MIRBuilder.getMF()); ToTruncate = defaultReg; } auto NewRegister = - GR->buildConstantInt(DefaultValue, MIRBuilder, PointerSizeType); + GTR->buildConstantInt(DefaultValue, MIRBuilder, PointerSizeType); MIRBuilder.buildCopy(defaultReg, NewRegister); } else { // If it could be in range, we need to load from the given builtin. auto Vec3Ty = - GR->getOrCreateSPIRVVectorType(PointerSizeType, 3, MIRBuilder); + GTR->getOrCreateSPIRVVectorType(PointerSizeType, 3, MIRBuilder); Register LoadedVector = - buildBuiltinVariableLoad(MIRBuilder, Vec3Ty, GR, BuiltinValue, + buildBuiltinVariableLoad(MIRBuilder, Vec3Ty, GTR, BuiltinValue, LLT::fixed_vector(3, PointerSize)); // Set up the vreg to extract the result to (possibly a new temporary one). Register Extracted = Call->ReturnRegister; if (!IsConstantIndex || PointerSize != ResultWidth) { Extracted = MRI->createGenericVirtualRegister(LLT::scalar(PointerSize)); - GR->assignSPIRVTypeToVReg(PointerSizeType, Extracted, MIRBuilder.getMF()); + GTR->assignSPIRVTypeToVReg(PointerSizeType, Extracted, + MIRBuilder.getMF()); } // Use Intrinsic::spv_extractelt so dynamic vs static extraction is // handled later: extr = spv_extractelt LoadedVector, IndexRegister. @@ -966,32 +967,32 @@ static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call, // If the index is dynamic, need check if it's < 3, and then use a select. if (!IsConstantIndex) { - insertAssignInstr(Extracted, nullptr, PointerSizeType, GR, MIRBuilder, + insertAssignInstr(Extracted, nullptr, PointerSizeType, GTR, MIRBuilder, *MRI); - auto IndexType = GR->getSPIRVTypeForVReg(IndexRegister); - auto BoolType = GR->getOrCreateSPIRVBoolType(MIRBuilder); + auto IndexType = GTR->getSPIRVTypeForVReg(IndexRegister); + auto BoolType = GTR->getOrCreateSPIRVBoolType(MIRBuilder); Register CompareRegister = MRI->createGenericVirtualRegister(LLT::scalar(1)); - GR->assignSPIRVTypeToVReg(BoolType, CompareRegister, MIRBuilder.getMF()); + GTR->assignSPIRVTypeToVReg(BoolType, CompareRegister, MIRBuilder.getMF()); // Use G_ICMP to check if idxVReg < 3. MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CompareRegister, IndexRegister, - GR->buildConstantInt(3, MIRBuilder, IndexType)); + GTR->buildConstantInt(3, MIRBuilder, IndexType)); // Get constant for the default value (0 or 1 depending on which // function). Register DefaultRegister = - GR->buildConstantInt(DefaultValue, MIRBuilder, PointerSizeType); + GTR->buildConstantInt(DefaultValue, MIRBuilder, PointerSizeType); // Get a register for the selection result (possibly a new temporary one). Register SelectionResult = Call->ReturnRegister; if (PointerSize != ResultWidth) { SelectionResult = MRI->createGenericVirtualRegister(LLT::scalar(PointerSize)); - GR->assignSPIRVTypeToVReg(PointerSizeType, SelectionResult, - MIRBuilder.getMF()); + GTR->assignSPIRVTypeToVReg(PointerSizeType, SelectionResult, + MIRBuilder.getMF()); } // Create the final G_SELECT to return the extracted value or the default. MIRBuilder.buildSelect(SelectionResult, CompareRegister, Extracted, @@ -1009,17 +1010,17 @@ static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call, static bool generateBuiltinVar(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { // Lookup the builtin variable record. const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; SPIRV::BuiltIn::BuiltIn Value = SPIRV::lookupGetBuiltin(Builtin->Name, Builtin->Set)->Value; if (Value == SPIRV::BuiltIn::GlobalInvocationId) - return genWorkgroupQuery(Call, MIRBuilder, GR, Value, 0); + return genWorkgroupQuery(Call, MIRBuilder, GTR, Value, 0); // Build a load instruction for the builtin variable. - unsigned BitWidth = GR->getScalarOrVectorBitWidth(Call->ReturnType); + unsigned BitWidth = GTR->getScalarOrVectorBitWidth(Call->ReturnType); LLT LLType; if (Call->ReturnType->getOpcode() == SPIRV::OpTypeVector) LLType = @@ -1027,13 +1028,13 @@ static bool generateBuiltinVar(const SPIRV::IncomingCall *Call, else LLType = LLT::scalar(BitWidth); - return buildBuiltinVariableLoad(MIRBuilder, Call->ReturnType, GR, Value, + return buildBuiltinVariableLoad(MIRBuilder, Call->ReturnType, GTR, Value, LLType, Call->ReturnRegister); } static bool generateAtomicInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { // Lookup the instruction opcode in the TableGen records. const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; unsigned Opcode = @@ -1043,24 +1044,24 @@ static bool generateAtomicInst(const SPIRV::IncomingCall *Call, case SPIRV::OpStore: return buildAtomicInitInst(Call, MIRBuilder); case SPIRV::OpAtomicLoad: - return buildAtomicLoadInst(Call, MIRBuilder, GR); + return buildAtomicLoadInst(Call, MIRBuilder, GTR); case SPIRV::OpAtomicStore: - return buildAtomicStoreInst(Call, MIRBuilder, GR); + return buildAtomicStoreInst(Call, MIRBuilder, GTR); case SPIRV::OpAtomicCompareExchange: case SPIRV::OpAtomicCompareExchangeWeak: - return buildAtomicCompareExchangeInst(Call, MIRBuilder, GR); + return buildAtomicCompareExchangeInst(Call, MIRBuilder, GTR); case SPIRV::OpAtomicIAdd: case SPIRV::OpAtomicISub: case SPIRV::OpAtomicOr: case SPIRV::OpAtomicXor: case SPIRV::OpAtomicAnd: case SPIRV::OpAtomicExchange: - return buildAtomicRMWInst(Call, Opcode, MIRBuilder, GR); + return buildAtomicRMWInst(Call, Opcode, MIRBuilder, GTR); case SPIRV::OpMemoryBarrier: - return buildBarrierInst(Call, SPIRV::OpMemoryBarrier, MIRBuilder, GR); + return buildBarrierInst(Call, SPIRV::OpMemoryBarrier, MIRBuilder, GTR); case SPIRV::OpAtomicFlagTestAndSet: case SPIRV::OpAtomicFlagClear: - return buildAtomicFlagInst(Call, Opcode, MIRBuilder, GR); + return buildAtomicFlagInst(Call, Opcode, MIRBuilder, GTR); default: return false; } @@ -1068,24 +1069,24 @@ static bool generateAtomicInst(const SPIRV::IncomingCall *Call, static bool generateBarrierInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { // Lookup the instruction opcode in the TableGen records. const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; unsigned Opcode = SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode; - return buildBarrierInst(Call, Opcode, MIRBuilder, GR); + return buildBarrierInst(Call, Opcode, MIRBuilder, GTR); } static bool generateDotOrFMulInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { - unsigned Opcode = GR->getSPIRVTypeForVReg(Call->Arguments[0])->getOpcode(); + SPIRVGlobalTypeRegistry *GTR) { + unsigned Opcode = GTR->getSPIRVTypeForVReg(Call->Arguments[0])->getOpcode(); bool IsVec = Opcode == SPIRV::OpTypeVector; // Use OpDot only in case of vector args and OpFMul in case of scalar args. MIRBuilder.buildInstr(IsVec ? SPIRV::OpDot : SPIRV::OpFMulS) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)) + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)) .addUse(Call->Arguments[0]) .addUse(Call->Arguments[1]); return true; @@ -1093,19 +1094,19 @@ static bool generateDotOrFMulInst(const SPIRV::IncomingCall *Call, static bool generateGetQueryInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { // Lookup the builtin record. SPIRV::BuiltIn::BuiltIn Value = SPIRV::lookupGetBuiltin(Call->Builtin->Name, Call->Builtin->Set)->Value; uint64_t IsDefault = (Value == SPIRV::BuiltIn::GlobalSize || Value == SPIRV::BuiltIn::WorkgroupSize || Value == SPIRV::BuiltIn::EnqueuedWorkgroupSize); - return genWorkgroupQuery(Call, MIRBuilder, GR, Value, IsDefault ? 1 : 0); + return genWorkgroupQuery(Call, MIRBuilder, GTR, Value, IsDefault ? 1 : 0); } static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { // Lookup the image size query component number in the TableGen records. const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; uint32_t Component = @@ -1118,27 +1119,28 @@ static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call, ? RetTy->getOperand(2).getImm() : 1; // Get the actual number of query result/size components. - SPIRVType *ImgType = GR->getSPIRVTypeForVReg(Call->Arguments[0]); + SPIRVType *ImgType = GTR->getSPIRVTypeForVReg(Call->Arguments[0]); unsigned NumActualRetComponents = getNumSizeComponents(ImgType); Register QueryResult = Call->ReturnRegister; SPIRVType *QueryResultType = Call->ReturnType; if (NumExpectedRetComponents != NumActualRetComponents) { QueryResult = MIRBuilder.getMRI()->createGenericVirtualRegister( LLT::fixed_vector(NumActualRetComponents, 32)); - SPIRVType *IntTy = GR->getOrCreateSPIRVIntegerType(32, MIRBuilder); - QueryResultType = GR->getOrCreateSPIRVVectorType( + SPIRVType *IntTy = GTR->getOrCreateSPIRVIntegerType(32, MIRBuilder); + QueryResultType = GTR->getOrCreateSPIRVVectorType( IntTy, NumActualRetComponents, MIRBuilder); - GR->assignSPIRVTypeToVReg(QueryResultType, QueryResult, MIRBuilder.getMF()); + GTR->assignSPIRVTypeToVReg(QueryResultType, QueryResult, + MIRBuilder.getMF()); } bool IsDimBuf = ImgType->getOperand(2).getImm() == SPIRV::Dim::DIM_Buffer; unsigned Opcode = IsDimBuf ? SPIRV::OpImageQuerySize : SPIRV::OpImageQuerySizeLod; auto MIB = MIRBuilder.buildInstr(Opcode) .addDef(QueryResult) - .addUse(GR->getSPIRVTypeID(QueryResultType)) + .addUse(GTR->getSPIRVTypeID(QueryResultType)) .addUse(Call->Arguments[0]); if (!IsDimBuf) - MIB.addUse(buildConstantIntReg(0, MIRBuilder, GR)); // Lod id. + MIB.addUse(buildConstantIntReg(0, MIRBuilder, GTR)); // Lod id. if (NumExpectedRetComponents == NumActualRetComponents) return true; if (NumExpectedRetComponents == 1) { @@ -1149,14 +1151,14 @@ static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call, "Invalid composite index!"); MIRBuilder.buildInstr(SPIRV::OpCompositeExtract) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)) + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)) .addUse(QueryResult) .addImm(ExtractedComposite); } else { // More than 1 component is expected, fill a new vector. auto MIB = MIRBuilder.buildInstr(SPIRV::OpVectorShuffle) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)) + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)) .addUse(QueryResult) .addUse(QueryResult); for (unsigned i = 0; i < NumExpectedRetComponents; ++i) @@ -1167,7 +1169,7 @@ static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call, static bool generateImageMiscQueryInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { assert(Call->ReturnType->getOpcode() == SPIRV::OpTypeInt && "Image samples query result must be of int type!"); @@ -1178,7 +1180,7 @@ static bool generateImageMiscQueryInst(const SPIRV::IncomingCall *Call, Register Image = Call->Arguments[0]; SPIRV::Dim::Dim ImageDimensionality = static_cast( - GR->getSPIRVTypeForVReg(Image)->getOperand(2).getImm()); + GTR->getSPIRVTypeForVReg(Image)->getOperand(2).getImm()); switch (Opcode) { case SPIRV::OpImageQuerySamples: @@ -1196,7 +1198,7 @@ static bool generateImageMiscQueryInst(const SPIRV::IncomingCall *Call, MIRBuilder.buildInstr(Opcode) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)) + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)) .addUse(Image); return true; } @@ -1236,49 +1238,49 @@ getSamplerFilterModeFromBitmask(unsigned Bitmask) { static bool generateReadImageInst(const StringRef DemangledCall, const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { Register Image = Call->Arguments[0]; MachineRegisterInfo *MRI = MIRBuilder.getMRI(); if (DemangledCall.contains_insensitive("ocl_sampler")) { Register Sampler = Call->Arguments[1]; - if (!GR->isScalarOfType(Sampler, SPIRV::OpTypeSampler) && + if (!GTR->isScalarOfType(Sampler, SPIRV::OpTypeSampler) && getDefInstrMaybeConstant(Sampler, MRI)->getOperand(1).isCImm()) { uint64_t SamplerMask = getIConstVal(Sampler, MRI); - Sampler = GR->buildConstantSampler( + Sampler = GTR->buildConstantSampler( Register(), getSamplerAddressingModeFromBitmask(SamplerMask), getSamplerParamFromBitmask(SamplerMask), getSamplerFilterModeFromBitmask(SamplerMask), MIRBuilder, - GR->getSPIRVTypeForVReg(Sampler)); + GTR->getSPIRVTypeForVReg(Sampler)); } - SPIRVType *ImageType = GR->getSPIRVTypeForVReg(Image); + SPIRVType *ImageType = GTR->getSPIRVTypeForVReg(Image); SPIRVType *SampledImageType = - GR->getOrCreateOpTypeSampledImage(ImageType, MIRBuilder); + GTR->getOrCreateOpTypeSampledImage(ImageType, MIRBuilder); Register SampledImage = MRI->createVirtualRegister(&SPIRV::IDRegClass); MIRBuilder.buildInstr(SPIRV::OpSampledImage) .addDef(SampledImage) - .addUse(GR->getSPIRVTypeID(SampledImageType)) + .addUse(GTR->getSPIRVTypeID(SampledImageType)) .addUse(Image) .addUse(Sampler); - Register Lod = GR->buildConstantFP(APFloat::getZero(APFloat::IEEEsingle()), - MIRBuilder); + Register Lod = GTR->buildConstantFP(APFloat::getZero(APFloat::IEEEsingle()), + MIRBuilder); SPIRVType *TempType = Call->ReturnType; bool NeedsExtraction = false; if (TempType->getOpcode() != SPIRV::OpTypeVector) { TempType = - GR->getOrCreateSPIRVVectorType(Call->ReturnType, 4, MIRBuilder); + GTR->getOrCreateSPIRVVectorType(Call->ReturnType, 4, MIRBuilder); NeedsExtraction = true; } - LLT LLType = LLT::scalar(GR->getScalarOrVectorBitWidth(TempType)); + LLT LLType = LLT::scalar(GTR->getScalarOrVectorBitWidth(TempType)); Register TempRegister = MRI->createGenericVirtualRegister(LLType); - GR->assignSPIRVTypeToVReg(TempType, TempRegister, MIRBuilder.getMF()); + GTR->assignSPIRVTypeToVReg(TempType, TempRegister, MIRBuilder.getMF()); MIRBuilder.buildInstr(SPIRV::OpImageSampleExplicitLod) .addDef(NeedsExtraction ? TempRegister : Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(TempType)) + .addUse(GTR->getSPIRVTypeID(TempType)) .addUse(SampledImage) .addUse(Call->Arguments[2]) // Coordinate. .addImm(SPIRV::ImageOperand::Lod) @@ -1287,13 +1289,13 @@ static bool generateReadImageInst(const StringRef DemangledCall, if (NeedsExtraction) MIRBuilder.buildInstr(SPIRV::OpCompositeExtract) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)) + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)) .addUse(TempRegister) .addImm(0); } else if (DemangledCall.contains_insensitive("msaa")) { MIRBuilder.buildInstr(SPIRV::OpImageRead) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)) + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)) .addUse(Image) .addUse(Call->Arguments[1]) // Coordinate. .addImm(SPIRV::ImageOperand::Sample) @@ -1301,7 +1303,7 @@ static bool generateReadImageInst(const StringRef DemangledCall, } else { MIRBuilder.buildInstr(SPIRV::OpImageRead) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)) + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)) .addUse(Image) .addUse(Call->Arguments[1]); // Coordinate. } @@ -1310,7 +1312,7 @@ static bool generateReadImageInst(const StringRef DemangledCall, static bool generateWriteImageInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { MIRBuilder.buildInstr(SPIRV::OpImageWrite) .addUse(Call->Arguments[0]) // Image. .addUse(Call->Arguments[1]) // Coordinate. @@ -1321,12 +1323,12 @@ static bool generateWriteImageInst(const SPIRV::IncomingCall *Call, static bool generateSampleImageInst(const StringRef DemangledCall, const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { if (Call->Builtin->Name.contains_insensitive( "__translate_sampler_initializer")) { // Build sampler literal. uint64_t Bitmask = getIConstVal(Call->Arguments[0], MIRBuilder.getMRI()); - Register Sampler = GR->buildConstantSampler( + Register Sampler = GTR->buildConstantSampler( Call->ReturnRegister, getSamplerAddressingModeFromBitmask(Bitmask), getSamplerParamFromBitmask(Bitmask), getSamplerFilterModeFromBitmask(Bitmask), MIRBuilder, Call->ReturnType); @@ -1334,16 +1336,16 @@ static bool generateSampleImageInst(const StringRef DemangledCall, } else if (Call->Builtin->Name.contains_insensitive("__spirv_SampledImage")) { // Create OpSampledImage. Register Image = Call->Arguments[0]; - SPIRVType *ImageType = GR->getSPIRVTypeForVReg(Image); + SPIRVType *ImageType = GTR->getSPIRVTypeForVReg(Image); SPIRVType *SampledImageType = - GR->getOrCreateOpTypeSampledImage(ImageType, MIRBuilder); + GTR->getOrCreateOpTypeSampledImage(ImageType, MIRBuilder); Register SampledImage = Call->ReturnRegister.isValid() ? Call->ReturnRegister : MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass); MIRBuilder.buildInstr(SPIRV::OpSampledImage) .addDef(SampledImage) - .addUse(GR->getSPIRVTypeID(SampledImageType)) + .addUse(GTR->getSPIRVTypeID(SampledImageType)) .addUse(Image) .addUse(Call->Arguments[1]); // Sampler. return true; @@ -1355,10 +1357,10 @@ static bool generateSampleImageInst(const StringRef DemangledCall, ReturnType = ReturnType.substr(ReturnType.find("_R") + 2); ReturnType = ReturnType.substr(0, ReturnType.find('(')); } - SPIRVType *Type = GR->getOrCreateSPIRVTypeByName(ReturnType, MIRBuilder); + SPIRVType *Type = GTR->getOrCreateSPIRVTypeByName(ReturnType, MIRBuilder); MIRBuilder.buildInstr(SPIRV::OpImageSampleExplicitLod) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Type)) + .addUse(GTR->getSPIRVTypeID(Type)) .addUse(Call->Arguments[0]) // Image. .addUse(Call->Arguments[1]) // Coordinate. .addImm(SPIRV::ImageOperand::Lod) @@ -1377,7 +1379,7 @@ static bool generateSelectInst(const SPIRV::IncomingCall *Call, static bool generateSpecConstantInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { // Lookup the instruction opcode in the TableGen records. const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; unsigned Opcode = @@ -1408,7 +1410,7 @@ static bool generateSpecConstantInst(const SPIRV::IncomingCall *Call, } auto MIB = MIRBuilder.buildInstr(Opcode) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)); + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)); if (Call->ReturnType->getOpcode() != SPIRV::OpTypeBool) { if (Const->getOpcode() == TargetOpcode::G_CONSTANT) @@ -1421,7 +1423,7 @@ static bool generateSpecConstantInst(const SPIRV::IncomingCall *Call, case SPIRV::OpSpecConstantComposite: { auto MIB = MIRBuilder.buildInstr(Opcode) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)); + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)); for (unsigned i = 0; i < Call->Arguments.size(); i++) MIB.addUse(Call->Arguments[i]); return true; @@ -1496,7 +1498,7 @@ static const Type *getBlockStructType(Register ParamReg, // TODO: maybe move to the global register. static SPIRVType * getOrCreateSPIRVDeviceEventPointer(MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { LLVMContext &Context = MIRBuilder.getMF().getFunction().getContext(); Type *OpaqueType = StructType::getTypeByName(Context, "spirv.DeviceEvent"); if (!OpaqueType) @@ -1506,16 +1508,16 @@ getOrCreateSPIRVDeviceEventPointer(MachineIRBuilder &MIRBuilder, unsigned SC0 = storageClassToAddressSpace(SPIRV::StorageClass::Function); unsigned SC1 = storageClassToAddressSpace(SPIRV::StorageClass::Generic); Type *PtrType = PointerType::get(PointerType::get(OpaqueType, SC0), SC1); - return GR->getOrCreateSPIRVType(PtrType, MIRBuilder); + return GTR->getOrCreateSPIRVType(PtrType, MIRBuilder); } static bool buildEnqueueKernel(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { MachineRegisterInfo *MRI = MIRBuilder.getMRI(); const DataLayout &DL = MIRBuilder.getDataLayout(); bool HasEvents = Call->Builtin->Name.find("events") != StringRef::npos; - const SPIRVType *Int32Ty = GR->getOrCreateSPIRVIntegerType(32, MIRBuilder); + const SPIRVType *Int32Ty = GTR->getOrCreateSPIRVIntegerType(32, MIRBuilder); // Make vararg instructions before OpEnqueueKernel. // Local sizes arguments: Sizes of block invoke arguments. Clang generates @@ -1534,21 +1536,21 @@ static bool buildEnqueueKernel(const SPIRV::IncomingCall *Call, const uint64_t LocalSizeNum = cast(LocalSizeTy)->getNumElements(); unsigned SC = storageClassToAddressSpace(SPIRV::StorageClass::Generic); - const LLT LLType = LLT::pointer(SC, GR->getPointerSize()); - const SPIRVType *PointerSizeTy = GR->getOrCreateSPIRVPointerType( + const LLT LLType = LLT::pointer(SC, GTR->getPointerSize()); + const SPIRVType *PointerSizeTy = GTR->getOrCreateSPIRVPointerType( Int32Ty, MIRBuilder, SPIRV::StorageClass::Function); for (unsigned I = 0; I < LocalSizeNum; ++I) { Register Reg = MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass); MIRBuilder.getMRI()->setType(Reg, LLType); - GR->assignSPIRVTypeToVReg(PointerSizeTy, Reg, MIRBuilder.getMF()); + GTR->assignSPIRVTypeToVReg(PointerSizeTy, Reg, MIRBuilder.getMF()); auto GEPInst = MIRBuilder.buildIntrinsic(Intrinsic::spv_gep, ArrayRef{Reg}, true); GEPInst - .addImm(GepMI->getOperand(2).getImm()) // In bound. - .addUse(ArrayMI->getOperand(0).getReg()) // Alloca. - .addUse(buildConstantIntReg(0, MIRBuilder, GR)) // Indices. - .addUse(buildConstantIntReg(I, MIRBuilder, GR)); + .addImm(GepMI->getOperand(2).getImm()) // In bound. + .addUse(ArrayMI->getOperand(0).getReg()) // Alloca. + .addUse(buildConstantIntReg(0, MIRBuilder, GTR)) // Indices. + .addUse(buildConstantIntReg(I, MIRBuilder, GTR)); LocalSizes.push_back(Reg); } } @@ -1556,7 +1558,7 @@ static bool buildEnqueueKernel(const SPIRV::IncomingCall *Call, // SPIRV OpEnqueueKernel instruction has 10+ arguments. auto MIB = MIRBuilder.buildInstr(SPIRV::OpEnqueueKernel) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Int32Ty)); + .addUse(GTR->getSPIRVTypeID(Int32Ty)); // Copy all arguments before block invoke function pointer. const unsigned BlockFIdx = HasEvents ? 6 : 3; @@ -1565,9 +1567,9 @@ static bool buildEnqueueKernel(const SPIRV::IncomingCall *Call, // If there are no event arguments in the original call, add dummy ones. if (!HasEvents) { - MIB.addUse(buildConstantIntReg(0, MIRBuilder, GR)); // Dummy num events. - Register NullPtr = GR->getOrCreateConstNullPtr( - MIRBuilder, getOrCreateSPIRVDeviceEventPointer(MIRBuilder, GR)); + MIB.addUse(buildConstantIntReg(0, MIRBuilder, GTR)); // Dummy num events. + Register NullPtr = GTR->getOrCreateConstNullPtr( + MIRBuilder, getOrCreateSPIRVDeviceEventPointer(MIRBuilder, GTR)); MIB.addUse(NullPtr); // Dummy wait events. MIB.addUse(NullPtr); // Dummy ret event. } @@ -1584,10 +1586,10 @@ static bool buildEnqueueKernel(const SPIRV::IncomingCall *Call, Type *PType = const_cast(getBlockStructType(BlockLiteralReg, MRI)); // TODO: these numbers should be obtained from block literal structure. // Param Size: Size of block literal structure. - MIB.addUse(buildConstantIntReg(DL.getTypeStoreSize(PType), MIRBuilder, GR)); + MIB.addUse(buildConstantIntReg(DL.getTypeStoreSize(PType), MIRBuilder, GTR)); // Param Aligment: Aligment of block literal structure. MIB.addUse( - buildConstantIntReg(DL.getPrefTypeAlign(PType).value(), MIRBuilder, GR)); + buildConstantIntReg(DL.getPrefTypeAlign(PType).value(), MIRBuilder, GTR)); for (unsigned i = 0; i < LocalSizes.size(); i++) MIB.addUse(LocalSizes[i]); @@ -1596,7 +1598,7 @@ static bool buildEnqueueKernel(const SPIRV::IncomingCall *Call, static bool generateEnqueueInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { // Lookup the instruction opcode in the TableGen records. const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; unsigned Opcode = @@ -1610,11 +1612,11 @@ static bool generateEnqueueInst(const SPIRV::IncomingCall *Call, case SPIRV::OpGetDefaultQueue: return MIRBuilder.buildInstr(Opcode) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)); + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)); case SPIRV::OpIsValidEvent: return MIRBuilder.buildInstr(Opcode) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)) + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)) .addUse(Call->Arguments[0]); case SPIRV::OpSetUserEventStatus: return MIRBuilder.buildInstr(Opcode) @@ -1627,13 +1629,13 @@ static bool generateEnqueueInst(const SPIRV::IncomingCall *Call, .addUse(Call->Arguments[2]); case SPIRV::OpBuildNDRange: { MachineRegisterInfo *MRI = MIRBuilder.getMRI(); - SPIRVType *PtrType = GR->getSPIRVTypeForVReg(Call->Arguments[0]); + SPIRVType *PtrType = GTR->getSPIRVTypeForVReg(Call->Arguments[0]); assert(PtrType->getOpcode() == SPIRV::OpTypePointer && PtrType->getOperand(2).isReg()); Register TypeReg = PtrType->getOperand(2).getReg(); - SPIRVType *StructType = GR->getSPIRVTypeForVReg(TypeReg); + SPIRVType *StructType = GTR->getSPIRVTypeForVReg(TypeReg); Register TmpReg = MRI->createVirtualRegister(&SPIRV::IDRegClass); - GR->assignSPIRVTypeToVReg(StructType, TmpReg, MIRBuilder.getMF()); + GTR->assignSPIRVTypeToVReg(StructType, TmpReg, MIRBuilder.getMF()); // Skip the first arg, it's the destination pointer. OpBuildNDRange takes // three other arguments, so pass zero constant on absence. unsigned NumArgs = Call->Arguments.size(); @@ -1644,7 +1646,7 @@ static bool generateEnqueueInst(const SPIRV::IncomingCall *Call, Register GlobalWorkOffset = NumArgs <= 3 ? Register(0) : Call->Arguments[1]; if (NumArgs < 4) { Register Const; - SPIRVType *SpvTy = GR->getSPIRVTypeForVReg(GlobalWorkSize); + SPIRVType *SpvTy = GTR->getSPIRVTypeForVReg(GlobalWorkSize); if (SpvTy->getOpcode() == SPIRV::OpTypePointer) { MachineInstr *DefInstr = MRI->getUniqueVRegDef(GlobalWorkSize); assert(DefInstr && isSpvIntrinsic(*DefInstr, Intrinsic::spv_gep) && @@ -1652,21 +1654,21 @@ static bool generateEnqueueInst(const SPIRV::IncomingCall *Call, Register GWSPtr = DefInstr->getOperand(3).getReg(); // TODO: Maybe simplify generation of the type of the fields. unsigned Size = Call->Builtin->Name.equals("ndrange_3D") ? 3 : 2; - unsigned BitWidth = GR->getPointerSize() == 64 ? 64 : 32; + unsigned BitWidth = GTR->getPointerSize() == 64 ? 64 : 32; Type *BaseTy = IntegerType::get( MIRBuilder.getMF().getFunction().getContext(), BitWidth); Type *FieldTy = ArrayType::get(BaseTy, Size); - SPIRVType *SpvFieldTy = GR->getOrCreateSPIRVType(FieldTy, MIRBuilder); + SPIRVType *SpvFieldTy = GTR->getOrCreateSPIRVType(FieldTy, MIRBuilder); GlobalWorkSize = MRI->createVirtualRegister(&SPIRV::IDRegClass); - GR->assignSPIRVTypeToVReg(SpvFieldTy, GlobalWorkSize, - MIRBuilder.getMF()); + GTR->assignSPIRVTypeToVReg(SpvFieldTy, GlobalWorkSize, + MIRBuilder.getMF()); MIRBuilder.buildInstr(SPIRV::OpLoad) .addDef(GlobalWorkSize) - .addUse(GR->getSPIRVTypeID(SpvFieldTy)) + .addUse(GTR->getSPIRVTypeID(SpvFieldTy)) .addUse(GWSPtr); - Const = GR->getOrCreateConsIntArray(0, MIRBuilder, SpvFieldTy); + Const = GTR->getOrCreateConsIntArray(0, MIRBuilder, SpvFieldTy); } else { - Const = GR->buildConstantInt(0, MIRBuilder, SpvTy); + Const = GTR->buildConstantInt(0, MIRBuilder, SpvTy); } if (!LocalWorkSize.isValid()) LocalWorkSize = Const; @@ -1684,7 +1686,7 @@ static bool generateEnqueueInst(const SPIRV::IncomingCall *Call, .addUse(TmpReg); } case SPIRV::OpEnqueueKernel: - return buildEnqueueKernel(Call, MIRBuilder, GR); + return buildEnqueueKernel(Call, MIRBuilder, GTR); default: return false; } @@ -1692,23 +1694,23 @@ static bool generateEnqueueInst(const SPIRV::IncomingCall *Call, static bool generateAsyncCopy(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { // Lookup the instruction opcode in the TableGen records. const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; unsigned Opcode = SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode; - auto Scope = buildConstantIntReg(SPIRV::Scope::Workgroup, MIRBuilder, GR); + auto Scope = buildConstantIntReg(SPIRV::Scope::Workgroup, MIRBuilder, GTR); switch (Opcode) { case SPIRV::OpGroupAsyncCopy: return MIRBuilder.buildInstr(Opcode) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)) + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)) .addUse(Scope) .addUse(Call->Arguments[0]) .addUse(Call->Arguments[1]) .addUse(Call->Arguments[2]) - .addUse(buildConstantIntReg(1, MIRBuilder, GR)) + .addUse(buildConstantIntReg(1, MIRBuilder, GTR)) .addUse(Call->Arguments[3]); case SPIRV::OpGroupWaitEvents: return MIRBuilder.buildInstr(Opcode) @@ -1723,7 +1725,7 @@ static bool generateAsyncCopy(const SPIRV::IncomingCall *Call, static bool generateConvertInst(const StringRef DemangledCall, const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { // Lookup the conversion builtin in the TableGen records. const SPIRV::ConvertBuiltin *Builtin = SPIRV::lookupConvertBuiltin(Call->Builtin->Name, Call->Builtin->Set); @@ -1737,9 +1739,9 @@ static bool generateConvertInst(const StringRef DemangledCall, {(unsigned)Builtin->RoundingMode}); unsigned Opcode = SPIRV::OpNop; - if (GR->isScalarOrVectorOfType(Call->Arguments[0], SPIRV::OpTypeInt)) { + if (GTR->isScalarOrVectorOfType(Call->Arguments[0], SPIRV::OpTypeInt)) { // Int -> ... - if (GR->isScalarOrVectorOfType(Call->ReturnRegister, SPIRV::OpTypeInt)) { + if (GTR->isScalarOrVectorOfType(Call->ReturnRegister, SPIRV::OpTypeInt)) { // Int -> Int if (Builtin->IsSaturated) Opcode = Builtin->IsDestinationSigned ? SPIRV::OpSatConvertUToS @@ -1747,22 +1749,22 @@ static bool generateConvertInst(const StringRef DemangledCall, else Opcode = Builtin->IsDestinationSigned ? SPIRV::OpUConvert : SPIRV::OpSConvert; - } else if (GR->isScalarOrVectorOfType(Call->ReturnRegister, - SPIRV::OpTypeFloat)) { + } else if (GTR->isScalarOrVectorOfType(Call->ReturnRegister, + SPIRV::OpTypeFloat)) { // Int -> Float bool IsSourceSigned = DemangledCall[DemangledCall.find_first_of('(') + 1] != 'u'; Opcode = IsSourceSigned ? SPIRV::OpConvertSToF : SPIRV::OpConvertUToF; } - } else if (GR->isScalarOrVectorOfType(Call->Arguments[0], - SPIRV::OpTypeFloat)) { + } else if (GTR->isScalarOrVectorOfType(Call->Arguments[0], + SPIRV::OpTypeFloat)) { // Float -> ... - if (GR->isScalarOrVectorOfType(Call->ReturnRegister, SPIRV::OpTypeInt)) + if (GTR->isScalarOrVectorOfType(Call->ReturnRegister, SPIRV::OpTypeInt)) // Float -> Int Opcode = Builtin->IsDestinationSigned ? SPIRV::OpConvertFToS : SPIRV::OpConvertFToU; - else if (GR->isScalarOrVectorOfType(Call->ReturnRegister, - SPIRV::OpTypeFloat)) + else if (GTR->isScalarOrVectorOfType(Call->ReturnRegister, + SPIRV::OpTypeFloat)) // Float -> Float Opcode = SPIRV::OpFConvert; } @@ -1772,14 +1774,14 @@ static bool generateConvertInst(const StringRef DemangledCall, MIRBuilder.buildInstr(Opcode) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)) + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)) .addUse(Call->Arguments[0]); return true; } static bool generateVectorLoadStoreInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { // Lookup the vector load/store builtin in the TableGen records. const SPIRV::VectorLoadStoreBuiltin *Builtin = SPIRV::lookupVectorLoadStoreBuiltin(Call->Builtin->Name, @@ -1788,7 +1790,7 @@ static bool generateVectorLoadStoreInst(const SPIRV::IncomingCall *Call, auto MIB = MIRBuilder.buildInstr(SPIRV::OpExtInst) .addDef(Call->ReturnRegister) - .addUse(GR->getSPIRVTypeID(Call->ReturnType)) + .addUse(GTR->getSPIRVTypeID(Call->ReturnType)) .addImm(static_cast(SPIRV::InstructionSet::OpenCL_std)) .addImm(Builtin->Number); for (auto Argument : Call->Arguments) @@ -1803,7 +1805,7 @@ static bool generateVectorLoadStoreInst(const SPIRV::IncomingCall *Call, static bool generateLoadStoreInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { // Lookup the instruction opcode in the TableGen records. const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; unsigned Opcode = @@ -1813,7 +1815,7 @@ static bool generateLoadStoreInst(const SPIRV::IncomingCall *Call, auto MIB = MIRBuilder.buildInstr(Opcode); if (IsLoad) { MIB.addDef(Call->ReturnRegister); - MIB.addUse(GR->getSPIRVTypeID(Call->ReturnType)); + MIB.addUse(GTR->getSPIRVTypeID(Call->ReturnType)); } // Add a pointer to the value to load/store. MIB.addUse(Call->Arguments[0]); @@ -1838,18 +1840,18 @@ std::optional lowerBuiltin(const StringRef DemangledCall, MachineIRBuilder &MIRBuilder, const Register OrigRet, const Type *OrigRetTy, const SmallVectorImpl &Args, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { LLVM_DEBUG(dbgs() << "Lowering builtin call: " << DemangledCall << "\n"); // SPIR-V type and return register. Register ReturnRegister = OrigRet; SPIRVType *ReturnType = nullptr; if (OrigRetTy && !OrigRetTy->isVoidTy()) { - ReturnType = GR->assignTypeToVReg(OrigRetTy, OrigRet, MIRBuilder); + ReturnType = GTR->assignTypeToVReg(OrigRetTy, OrigRet, MIRBuilder); } else if (OrigRetTy && OrigRetTy->isVoidTy()) { ReturnRegister = MIRBuilder.getMRI()->createVirtualRegister(&IDRegClass); MIRBuilder.getMRI()->setType(ReturnRegister, LLT::scalar(32)); - ReturnType = GR->assignTypeToVReg(OrigRetTy, ReturnRegister, MIRBuilder); + ReturnType = GTR->assignTypeToVReg(OrigRetTy, ReturnRegister, MIRBuilder); } // Lookup the builtin in the TableGen records. @@ -1870,45 +1872,45 @@ std::optional lowerBuiltin(const StringRef DemangledCall, // Match the builtin with implementation based on the grouping. switch (Call->Builtin->Group) { case SPIRV::Extended: - return generateExtInst(Call.get(), MIRBuilder, GR); + return generateExtInst(Call.get(), MIRBuilder, GTR); case SPIRV::Relational: - return generateRelationalInst(Call.get(), MIRBuilder, GR); + return generateRelationalInst(Call.get(), MIRBuilder, GTR); case SPIRV::Group: - return generateGroupInst(Call.get(), MIRBuilder, GR); + return generateGroupInst(Call.get(), MIRBuilder, GTR); case SPIRV::Variable: - return generateBuiltinVar(Call.get(), MIRBuilder, GR); + return generateBuiltinVar(Call.get(), MIRBuilder, GTR); case SPIRV::Atomic: - return generateAtomicInst(Call.get(), MIRBuilder, GR); + return generateAtomicInst(Call.get(), MIRBuilder, GTR); case SPIRV::Barrier: - return generateBarrierInst(Call.get(), MIRBuilder, GR); + return generateBarrierInst(Call.get(), MIRBuilder, GTR); case SPIRV::Dot: - return generateDotOrFMulInst(Call.get(), MIRBuilder, GR); + return generateDotOrFMulInst(Call.get(), MIRBuilder, GTR); case SPIRV::GetQuery: - return generateGetQueryInst(Call.get(), MIRBuilder, GR); + return generateGetQueryInst(Call.get(), MIRBuilder, GTR); case SPIRV::ImageSizeQuery: - return generateImageSizeQueryInst(Call.get(), MIRBuilder, GR); + return generateImageSizeQueryInst(Call.get(), MIRBuilder, GTR); case SPIRV::ImageMiscQuery: - return generateImageMiscQueryInst(Call.get(), MIRBuilder, GR); + return generateImageMiscQueryInst(Call.get(), MIRBuilder, GTR); case SPIRV::ReadImage: - return generateReadImageInst(DemangledCall, Call.get(), MIRBuilder, GR); + return generateReadImageInst(DemangledCall, Call.get(), MIRBuilder, GTR); case SPIRV::WriteImage: - return generateWriteImageInst(Call.get(), MIRBuilder, GR); + return generateWriteImageInst(Call.get(), MIRBuilder, GTR); case SPIRV::SampleImage: - return generateSampleImageInst(DemangledCall, Call.get(), MIRBuilder, GR); + return generateSampleImageInst(DemangledCall, Call.get(), MIRBuilder, GTR); case SPIRV::Select: return generateSelectInst(Call.get(), MIRBuilder); case SPIRV::SpecConstant: - return generateSpecConstantInst(Call.get(), MIRBuilder, GR); + return generateSpecConstantInst(Call.get(), MIRBuilder, GTR); case SPIRV::Enqueue: - return generateEnqueueInst(Call.get(), MIRBuilder, GR); + return generateEnqueueInst(Call.get(), MIRBuilder, GTR); case SPIRV::AsyncCopy: - return generateAsyncCopy(Call.get(), MIRBuilder, GR); + return generateAsyncCopy(Call.get(), MIRBuilder, GTR); case SPIRV::Convert: - return generateConvertInst(DemangledCall, Call.get(), MIRBuilder, GR); + return generateConvertInst(DemangledCall, Call.get(), MIRBuilder, GTR); case SPIRV::VectorLoadStore: - return generateVectorLoadStoreInst(Call.get(), MIRBuilder, GR); + return generateVectorLoadStoreInst(Call.get(), MIRBuilder, GTR); case SPIRV::LoadStore: - return generateLoadStoreInst(Call.get(), MIRBuilder, GR); + return generateLoadStoreInst(Call.get(), MIRBuilder, GTR); } return false; } @@ -2009,41 +2011,41 @@ static const TargetExtType *parseToTargetExtType(const Type *OpaqueType, static SPIRVType *getNonParameterizedType(const TargetExtType *ExtensionType, const SPIRV::BuiltinType *TypeRecord, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { unsigned Opcode = TypeRecord->Opcode; // Create or get an existing type from GlobalRegistry. - return GR->getOrCreateOpTypeByOpcode(ExtensionType, MIRBuilder, Opcode); + return GTR->getOrCreateOpTypeByOpcode(ExtensionType, MIRBuilder, Opcode); } static SPIRVType *getSamplerType(MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { // Create or get an existing type from GlobalRegistry. - return GR->getOrCreateOpTypeSampler(MIRBuilder); + return GTR->getOrCreateOpTypeSampler(MIRBuilder); } static SPIRVType *getPipeType(const TargetExtType *ExtensionType, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { assert(ExtensionType->getNumIntParameters() == 1 && "Invalid number of parameters for SPIR-V pipe builtin!"); // Create or get an existing type from GlobalRegistry. - return GR->getOrCreateOpTypePipe(MIRBuilder, - SPIRV::AccessQualifier::AccessQualifier( - ExtensionType->getIntParameter(0))); + return GTR->getOrCreateOpTypePipe(MIRBuilder, + SPIRV::AccessQualifier::AccessQualifier( + ExtensionType->getIntParameter(0))); } static SPIRVType * getImageType(const TargetExtType *ExtensionType, const SPIRV::AccessQualifier::AccessQualifier Qualifier, - MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR) { + MachineIRBuilder &MIRBuilder, SPIRVGlobalTypeRegistry *GTR) { assert(ExtensionType->getNumTypeParameters() == 1 && "SPIR-V image builtin type must have sampled type parameter!"); const SPIRVType *SampledType = - GR->getOrCreateSPIRVType(ExtensionType->getTypeParameter(0), MIRBuilder); + GTR->getOrCreateSPIRVType(ExtensionType->getTypeParameter(0), MIRBuilder); assert(ExtensionType->getNumIntParameters() == 7 && "Invalid number of parameters for SPIR-V image builtin!"); // Create or get an existing type from GlobalRegistry. - return GR->getOrCreateOpTypeImage( + return GTR->getOrCreateOpTypeImage( MIRBuilder, SampledType, SPIRV::Dim::Dim(ExtensionType->getIntParameter(0)), ExtensionType->getIntParameter(1), ExtensionType->getIntParameter(2), @@ -2057,18 +2059,18 @@ getImageType(const TargetExtType *ExtensionType, static SPIRVType *getSampledImageType(const TargetExtType *OpaqueType, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { SPIRVType *OpaqueImageType = getImageType( - OpaqueType, SPIRV::AccessQualifier::ReadOnly, MIRBuilder, GR); + OpaqueType, SPIRV::AccessQualifier::ReadOnly, MIRBuilder, GTR); // Create or get an existing type from GlobalRegistry. - return GR->getOrCreateOpTypeSampledImage(OpaqueImageType, MIRBuilder); + return GTR->getOrCreateOpTypeSampledImage(OpaqueImageType, MIRBuilder); } namespace SPIRV { SPIRVType *lowerBuiltinType(const Type *OpaqueType, SPIRV::AccessQualifier::AccessQualifier AccessQual, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { // In LLVM IR, SPIR-V and OpenCL builtin types are represented as either // target(...) target extension types or pointers-to-opaque-structs. The // approach relying on structs is deprecated and works only in the non-opaque @@ -2098,30 +2100,30 @@ SPIRVType *lowerBuiltinType(const Type *OpaqueType, SPIRVType *TargetType; switch (TypeRecord->Opcode) { case SPIRV::OpTypeImage: - TargetType = getImageType(BuiltinType, AccessQual, MIRBuilder, GR); + TargetType = getImageType(BuiltinType, AccessQual, MIRBuilder, GTR); break; case SPIRV::OpTypePipe: - TargetType = getPipeType(BuiltinType, MIRBuilder, GR); + TargetType = getPipeType(BuiltinType, MIRBuilder, GTR); break; case SPIRV::OpTypeDeviceEvent: - TargetType = GR->getOrCreateOpTypeDeviceEvent(MIRBuilder); + TargetType = GTR->getOrCreateOpTypeDeviceEvent(MIRBuilder); break; case SPIRV::OpTypeSampler: - TargetType = getSamplerType(MIRBuilder, GR); + TargetType = getSamplerType(MIRBuilder, GTR); break; case SPIRV::OpTypeSampledImage: - TargetType = getSampledImageType(BuiltinType, MIRBuilder, GR); + TargetType = getSampledImageType(BuiltinType, MIRBuilder, GTR); break; default: TargetType = - getNonParameterizedType(BuiltinType, TypeRecord, MIRBuilder, GR); + getNonParameterizedType(BuiltinType, TypeRecord, MIRBuilder, GTR); break; } // Emit OpName instruction if a new OpType<...> instruction was added // (equivalent type was not found in GlobalRegistry). if (NumStartingVRegs < MIRBuilder.getMRI()->getNumVirtRegs()) - buildOpName(GR->getSPIRVTypeID(TargetType), Name, MIRBuilder); + buildOpName(GTR->getSPIRVTypeID(TargetType), Name, MIRBuilder); return TargetType; } diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.h b/llvm/lib/Target/SPIRV/SPIRVBuiltins.h index 7ee5c49dc5b3..ca2d49d5455e 100644 --- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.h +++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.h @@ -13,7 +13,7 @@ #ifndef LLVM_LIB_TARGET_SPIRV_SPIRVBUILTINS_H #define LLVM_LIB_TARGET_SPIRV_SPIRVBUILTINS_H -#include "SPIRVGlobalRegistry.h" +#include "Registries/SPIRVGlobalTypeRegistry.h" #include "llvm/CodeGen/GlobalISel/CallLowering.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" @@ -36,11 +36,11 @@ std::optional lowerBuiltin(const StringRef DemangledCall, MachineIRBuilder &MIRBuilder, const Register OrigRet, const Type *OrigRetTy, const SmallVectorImpl &Args, - SPIRVGlobalRegistry *GR); + SPIRVGlobalTypeRegistry *GTR); /// Handles the translation of the provided special opaque/builtin type \p Type /// to SPIR-V type. Generates the corresponding machine instructions for the /// target type or gets the already existing OpType<...> register from the -/// global registry \p GR. +/// global registry \p GTR. /// /// \return A machine instruction representing the OpType<...> SPIR-V type. /// @@ -48,7 +48,7 @@ std::optional lowerBuiltin(const StringRef DemangledCall, SPIRVType *lowerBuiltinType(const Type *Type, AccessQualifier::AccessQualifier AccessQual, MachineIRBuilder &MIRBuilder, - SPIRVGlobalRegistry *GR); + SPIRVGlobalTypeRegistry *GTR); } // namespace SPIRV } // namespace llvm #endif // LLVM_LIB_TARGET_SPIRV_SPIRVBUILTINS_H diff --git a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp index 8b618686ee7d..8e6af77c21a6 100644 --- a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp @@ -15,7 +15,7 @@ #include "MCTargetDesc/SPIRVBaseInfo.h" #include "SPIRV.h" #include "SPIRVBuiltins.h" -#include "SPIRVGlobalRegistry.h" +#include "Registries/SPIRVGlobalTypeRegistry.h" #include "SPIRVISelLowering.h" #include "SPIRVRegisterInfo.h" #include "SPIRVSubtarget.h" @@ -26,8 +26,8 @@ using namespace llvm; SPIRVCallLowering::SPIRVCallLowering(const SPIRVTargetLowering &TLI, - SPIRVGlobalRegistry *GR) - : CallLowering(&TLI), GR(GR) {} + SPIRVGlobalTypeRegistry *GTR) + : CallLowering(&TLI), GTR(GTR) {} bool SPIRVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef VRegs, @@ -217,8 +217,9 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef> VRegs, FunctionLoweringInfo &FLI) const { - assert(GR && "Must initialize the SPIRV type registry before lowering args."); - GR->setCurrentFunc(MIRBuilder.getMF()); + assert(GTR && + "Must initialize the SPIRV type registry before lowering args."); + GTR->setCurrentFunc(MIRBuilder.getMF()); // Assign types and names to all args, and store their types for later. FunctionType *FTy = getOriginalFunctionType(F); @@ -232,8 +233,8 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, return false; SPIRV::AccessQualifier::AccessQualifier ArgAccessQual = getArgAccessQual(F, i); - auto *SpirvTy = GR->assignTypeToVReg(getArgType(F, i), VRegs[i][0], - MIRBuilder, ArgAccessQual); + auto *SpirvTy = GTR->assignTypeToVReg(getArgType(F, i), VRegs[i][0], + MIRBuilder, ArgAccessQual); ArgTypeVRegs.push_back(SpirvTy); if (Arg.hasName()) @@ -305,9 +306,10 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(32)); MRI->setRegClass(FuncVReg, &SPIRV::IDRegClass); if (F.isDeclaration()) - GR->add(&F, &MIRBuilder.getMF(), FuncVReg); - SPIRVType *RetTy = GR->getOrCreateSPIRVType(FTy->getReturnType(), MIRBuilder); - SPIRVType *FuncTy = GR->getOrCreateOpTypeFunctionWithArgs( + GTR->add(&F, &MIRBuilder.getMF(), FuncVReg); + SPIRVType *RetTy = + GTR->getOrCreateSPIRVType(FTy->getReturnType(), MIRBuilder); + SPIRVType *FuncTy = GTR->getOrCreateOpTypeFunctionWithArgs( FTy, RetTy, ArgTypeVRegs, MIRBuilder); // Build the OpTypeFunction declaring it. @@ -315,9 +317,9 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, MIRBuilder.buildInstr(SPIRV::OpFunction) .addDef(FuncVReg) - .addUse(GR->getSPIRVTypeID(RetTy)) + .addUse(GTR->getSPIRVTypeID(RetTy)) .addImm(FuncControl) - .addUse(GR->getSPIRVTypeID(FuncTy)); + .addUse(GTR->getSPIRVTypeID(FuncTy)); // Add OpFunctionParameters. int i = 0; @@ -326,9 +328,9 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, MRI->setRegClass(VRegs[i][0], &SPIRV::IDRegClass); MIRBuilder.buildInstr(SPIRV::OpFunctionParameter) .addDef(VRegs[i][0]) - .addUse(GR->getSPIRVTypeID(ArgTypeVRegs[i])); + .addUse(GTR->getSPIRVTypeID(ArgTypeVRegs[i])); if (F.isDeclaration()) - GR->add(&Arg, &MIRBuilder.getMF(), VRegs[i][0]); + GTR->add(&Arg, &MIRBuilder.getMF(), VRegs[i][0]); i++; } // Name the function. @@ -359,7 +361,7 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, if (Info.OrigRet.Regs.size() > 1) return false; MachineFunction &MF = MIRBuilder.getMF(); - GR->setCurrentFunc(MF); + GTR->setCurrentFunc(MF); FunctionType *FTy = nullptr; const Function *CF = nullptr; @@ -389,16 +391,16 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, for (auto Arg : Info.OrigArgs) { assert(Arg.Regs.size() == 1 && "Call arg has multiple VRegs"); ArgVRegs.push_back(Arg.Regs[0]); - SPIRVType *SPIRVTy = GR->getOrCreateSPIRVType(Arg.Ty, MIRBuilder); - GR->assignSPIRVTypeToVReg(SPIRVTy, Arg.Regs[0], MIRBuilder.getMF()); + SPIRVType *SPIRVTy = GTR->getOrCreateSPIRVType(Arg.Ty, MIRBuilder); + GTR->assignSPIRVTypeToVReg(SPIRVTy, Arg.Regs[0], MIRBuilder.getMF()); } if (auto Res = SPIRV::lowerBuiltin( DemangledName, SPIRV::InstructionSet::OpenCL_std, MIRBuilder, - ResVReg, OrigRetTy, ArgVRegs, GR)) + ResVReg, OrigRetTy, ArgVRegs, GTR)) return *Res; } if (CF && CF->isDeclaration() && - !GR->find(CF, &MIRBuilder.getMF()).isValid()) { + !GTR->find(CF, &MIRBuilder.getMF()).isValid()) { // Emit the type info and forward function declaration to the first MBB // to ensure VReg definition dependencies are valid across all MBBs. MachineIRBuilder FirstBlockBuilder; @@ -423,12 +425,12 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, if (!ResVReg.isValid()) ResVReg = MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass); SPIRVType *RetType = - GR->assignTypeToVReg(FTy->getReturnType(), ResVReg, MIRBuilder); + GTR->assignTypeToVReg(FTy->getReturnType(), ResVReg, MIRBuilder); // Emit the OpFunctionCall and its args. auto MIB = MIRBuilder.buildInstr(SPIRV::OpFunctionCall) .addDef(ResVReg) - .addUse(GR->getSPIRVTypeID(RetType)) + .addUse(GTR->getSPIRVTypeID(RetType)) .add(Info.Callee); for (const auto &Arg : Info.OrigArgs) { diff --git a/llvm/lib/Target/SPIRV/SPIRVCallLowering.h b/llvm/lib/Target/SPIRV/SPIRVCallLowering.h index c2d6ad82d507..536139c38edc 100644 --- a/llvm/lib/Target/SPIRV/SPIRVCallLowering.h +++ b/llvm/lib/Target/SPIRV/SPIRVCallLowering.h @@ -13,21 +13,22 @@ #ifndef LLVM_LIB_TARGET_SPIRV_SPIRVCALLLOWERING_H #define LLVM_LIB_TARGET_SPIRV_SPIRVCALLLOWERING_H -#include "SPIRVGlobalRegistry.h" +#include "Registries/SPIRVGlobalTypeRegistry.h" #include "llvm/CodeGen/GlobalISel/CallLowering.h" namespace llvm { -class SPIRVGlobalRegistry; +class SPIRVGlobalTypeRegistry; class SPIRVTargetLowering; class SPIRVCallLowering : public CallLowering { private: // Used to create and assign function, argument, and return type information. - SPIRVGlobalRegistry *GR; + SPIRVGlobalTypeRegistry *GTR; public: - SPIRVCallLowering(const SPIRVTargetLowering &TLI, SPIRVGlobalRegistry *GR); + SPIRVCallLowering(const SPIRVTargetLowering &TLI, + SPIRVGlobalTypeRegistry *GTR); // Built OpReturn or OpReturnValue. bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val, diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index 5507e9254fae..636bb2e33e66 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -13,7 +13,7 @@ //===----------------------------------------------------------------------===// #include "SPIRV.h" -#include "SPIRVGlobalRegistry.h" +#include "Registries/SPIRVGlobalTypeRegistry.h" #include "SPIRVInstrInfo.h" #include "SPIRVRegisterBankInfo.h" #include "SPIRVRegisterInfo.h" @@ -47,7 +47,7 @@ class SPIRVInstructionSelector : public InstructionSelector { const SPIRVInstrInfo &TII; const SPIRVRegisterInfo &TRI; const RegisterBankInfo &RBI; - SPIRVGlobalRegistry &GR; + SPIRVGlobalTypeRegistry >R; MachineRegisterInfo *MRI; public: @@ -190,7 +190,8 @@ SPIRVInstructionSelector::SPIRVInstructionSelector(const SPIRVTargetMachine &TM, const SPIRVSubtarget &ST, const RegisterBankInfo &RBI) : InstructionSelector(), STI(ST), TII(*ST.getInstrInfo()), - TRI(*ST.getRegisterInfo()), RBI(RBI), GR(*ST.getSPIRVGlobalRegistry()), + TRI(*ST.getRegisterInfo()), RBI(RBI), + GTR(*ST.getSPIRVGlobalTypeRegistry()), #define GET_GLOBALISEL_PREDICATES_INIT #include "SPIRVGenGlobalISel.inc" #undef GET_GLOBALISEL_PREDICATES_INIT @@ -205,7 +206,7 @@ void SPIRVInstructionSelector::setupMF(MachineFunction &MF, GISelKnownBits *KB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) { MRI = &MF.getRegInfo(); - GR.setCurrentFunc(MF); + GTR.setCurrentFunc(MF); InstructionSelector::setupMF(MF, KB, CoverageInfo, PSI, BFI); } @@ -248,7 +249,7 @@ bool SPIRVInstructionSelector::select(MachineInstr &I) { // from parent occurs here. Instr-specific selection happens in spvSelect(). bool HasDefs = I.getNumDefs() > 0; Register ResVReg = HasDefs ? I.getOperand(0).getReg() : Register(0); - SPIRVType *ResType = HasDefs ? GR.getSPIRVTypeForVReg(ResVReg) : nullptr; + SPIRVType *ResType = HasDefs ? GTR.getSPIRVTypeForVReg(ResVReg) : nullptr; assert(!HasDefs || ResType || I.getOpcode() == TargetOpcode::G_GLOBAL_VALUE); if (spvSelect(ResVReg, ResType, I)) { if (HasDefs) // Make all vregs 32 bits (for SPIR-V IDs). @@ -286,7 +287,7 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg, MachineBasicBlock &BB = *I.getParent(); auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorShuffle)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .addUse(I.getOperand(1).getReg()) .addUse(I.getOperand(2).getReg()); for (auto V : I.getOperand(3).getShuffleMask()) @@ -442,11 +443,12 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg, (*II).getOpcode() == TargetOpcode::COPY || (*II).getOpcode() == SPIRV::OpVariable) && isImm(I.getOperand(2), MRI)); - Register Idx = buildZerosVal(GR.getOrCreateSPIRVIntegerType(32, I, TII), I); + Register Idx = + buildZerosVal(GTR.getOrCreateSPIRVIntegerType(32, I, TII), I); MachineBasicBlock &BB = *I.getParent(); auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSpecConstantOp)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .addImm(static_cast( SPIRV::Opcode::InBoundsPtrAccessChain)) .addUse(GV) @@ -516,7 +518,7 @@ bool SPIRVInstructionSelector::selectExtInst(Register ResVReg, MachineBasicBlock &BB = *I.getParent(); auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .addImm(static_cast(Set)) .addImm(Opcode); const unsigned NumOps = I.getNumOperands(); @@ -535,7 +537,7 @@ bool SPIRVInstructionSelector::selectUnOpWithSrc(Register ResVReg, unsigned Opcode) const { return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .addUse(SrcReg) .constrainAllUses(TII, TRI, RBI); } @@ -595,7 +597,7 @@ bool SPIRVInstructionSelector::selectLoad(Register ResVReg, Register Ptr = I.getOperand(1 + OpOffset).getReg(); auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .addUse(Ptr); if (!I.getNumMemOperands()) { assert(I.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS); @@ -632,27 +634,27 @@ bool SPIRVInstructionSelector::selectMemOperation(Register ResVReg, assert(I.getOperand(1).isReg() && I.getOperand(2).isReg()); unsigned Val = getIConstVal(I.getOperand(1).getReg(), MRI); unsigned Num = getIConstVal(I.getOperand(2).getReg(), MRI); - SPIRVType *ValTy = GR.getOrCreateSPIRVIntegerType(8, I, TII); - SPIRVType *ArrTy = GR.getOrCreateSPIRVArrayType(ValTy, Num, I, TII); - Register Const = GR.getOrCreateConsIntArray(Val, I, ArrTy, TII); - SPIRVType *VarTy = GR.getOrCreateSPIRVPointerType( + SPIRVType *ValTy = GTR.getOrCreateSPIRVIntegerType(8, I, TII); + SPIRVType *ArrTy = GTR.getOrCreateSPIRVArrayType(ValTy, Num, I, TII); + Register Const = GTR.getOrCreateConsIntArray(Val, I, ArrTy, TII); + SPIRVType *VarTy = GTR.getOrCreateSPIRVPointerType( ArrTy, I, TII, SPIRV::StorageClass::UniformConstant); // TODO: check if we have such GV, add init, use buildGlobalVariable. Type *LLVMArrTy = ArrayType::get( - IntegerType::get(GR.CurMF->getFunction().getContext(), 8), Num); + IntegerType::get(GTR.CurMF->getFunction().getContext(), 8), Num); GlobalVariable *GV = new GlobalVariable(LLVMArrTy, true, GlobalValue::InternalLinkage); Register VarReg = MRI->createGenericVirtualRegister(LLT::scalar(32)); - GR.add(GV, GR.CurMF, VarReg); + GTR.add(GV, GTR.CurMF, VarReg); buildOpDecorate(VarReg, I, TII, SPIRV::Decoration::Constant, {}); BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpVariable)) .addDef(VarReg) - .addUse(GR.getSPIRVTypeID(VarTy)) + .addUse(GTR.getSPIRVTypeID(VarTy)) .addImm(SPIRV::StorageClass::UniformConstant) .addUse(Const) .constrainAllUses(TII, TRI, RBI); - SPIRVType *SourceTy = GR.getOrCreateSPIRVPointerType( + SPIRVType *SourceTy = GTR.getOrCreateSPIRVPointerType( ValTy, I, TII, SPIRV::StorageClass::UniformConstant); SrcReg = MRI->createGenericVirtualRegister(LLT::scalar(32)); selectUnOpWithSrc(SrcReg, SourceTy, I, VarReg, SPIRV::OpBitcast); @@ -682,14 +684,14 @@ bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg, Register Ptr = I.getOperand(1).getReg(); // TODO: Changed as it's implemented in the translator. See test/atomicrmw.ll // auto ScSem = - // getMemSemanticsForStorageClass(GR.getPointerStorageClass(Ptr)); + // getMemSemanticsForStorageClass(GTR.getPointerStorageClass(Ptr)); AtomicOrdering AO = MemOp->getSuccessOrdering(); uint32_t MemSem = static_cast(getMemSemantics(AO)); Register MemSemReg = buildI32Constant(MemSem /*| ScSem*/, I); return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(NewOpcode)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .addUse(Ptr) .addUse(ScopeReg) .addUse(MemSemReg) @@ -725,7 +727,7 @@ bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg, ScopeReg = buildI32Constant(Scope, I); unsigned ScSem = static_cast( - getMemSemanticsForStorageClass(GR.getPointerStorageClass(Ptr))); + getMemSemanticsForStorageClass(GTR.getPointerStorageClass(Ptr))); AtomicOrdering AO = MemOp->getSuccessOrdering(); unsigned MemSemEq = static_cast(getMemSemantics(AO)) | ScSem; MemSemEqReg = buildI32Constant(MemSemEq, I); @@ -741,13 +743,13 @@ bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg, Register Cmp = I.getOperand(3).getReg(); Register Val = I.getOperand(4).getReg(); - SPIRVType *SpvValTy = GR.getSPIRVTypeForVReg(Val); + SPIRVType *SpvValTy = GTR.getSPIRVTypeForVReg(Val); Register ACmpRes = MRI->createVirtualRegister(&SPIRV::IDRegClass); const DebugLoc &DL = I.getDebugLoc(); bool Result = BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpAtomicCompareExchange)) .addDef(ACmpRes) - .addUse(GR.getSPIRVTypeID(SpvValTy)) + .addUse(GTR.getSPIRVTypeID(SpvValTy)) .addUse(Ptr) .addUse(ScopeReg) .addUse(MemSemEqReg) @@ -756,24 +758,24 @@ bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg, .addUse(Cmp) .constrainAllUses(TII, TRI, RBI); Register CmpSuccReg = MRI->createVirtualRegister(&SPIRV::IDRegClass); - SPIRVType *BoolTy = GR.getOrCreateSPIRVBoolType(I, TII); + SPIRVType *BoolTy = GTR.getOrCreateSPIRVBoolType(I, TII); Result |= BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpIEqual)) .addDef(CmpSuccReg) - .addUse(GR.getSPIRVTypeID(BoolTy)) + .addUse(GTR.getSPIRVTypeID(BoolTy)) .addUse(ACmpRes) .addUse(Cmp) .constrainAllUses(TII, TRI, RBI); Register TmpReg = MRI->createVirtualRegister(&SPIRV::IDRegClass); Result |= BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert)) .addDef(TmpReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .addUse(ACmpRes) - .addUse(GR.getOrCreateUndef(I, ResType, TII)) + .addUse(GTR.getOrCreateUndef(I, ResType, TII)) .addImm(0) .constrainAllUses(TII, TRI, RBI); Result |= BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .addUse(CmpSuccReg) .addUse(TmpReg) .addImm(1) @@ -809,22 +811,22 @@ bool SPIRVInstructionSelector::selectAddrSpaceCast(Register ResVReg, isSpvIntrinsic(*UIs.begin(), Intrinsic::spv_init_global))) { Register NewReg = I.getOperand(1).getReg(); MachineBasicBlock &BB = *I.getParent(); - SPIRVType *SpvBaseTy = GR.getOrCreateSPIRVIntegerType(8, I, TII); - ResType = GR.getOrCreateSPIRVPointerType(SpvBaseTy, I, TII, - SPIRV::StorageClass::Generic); + SPIRVType *SpvBaseTy = GTR.getOrCreateSPIRVIntegerType(8, I, TII); + ResType = GTR.getOrCreateSPIRVPointerType(SpvBaseTy, I, TII, + SPIRV::StorageClass::Generic); bool Result = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSpecConstantOp)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .addImm(static_cast(SPIRV::Opcode::PtrCastToGeneric)) .addUse(NewReg) .constrainAllUses(TII, TRI, RBI); return Result; } Register SrcPtr = I.getOperand(1).getReg(); - SPIRVType *SrcPtrTy = GR.getSPIRVTypeForVReg(SrcPtr); - SPIRV::StorageClass::StorageClass SrcSC = GR.getPointerStorageClass(SrcPtr); - SPIRV::StorageClass::StorageClass DstSC = GR.getPointerStorageClass(ResVReg); + SPIRVType *SrcPtrTy = GTR.getSPIRVTypeForVReg(SrcPtr); + SPIRV::StorageClass::StorageClass SrcSC = GTR.getPointerStorageClass(SrcPtr); + SPIRV::StorageClass::StorageClass DstSC = GTR.getPointerStorageClass(ResVReg); // Casting from an eligable pointer to Generic. if (DstSC == SPIRV::StorageClass::Generic && isGenericCastablePtr(SrcSC)) @@ -835,18 +837,18 @@ bool SPIRVInstructionSelector::selectAddrSpaceCast(Register ResVReg, // Casting between 2 eligable pointers using Generic as an intermediary. if (isGenericCastablePtr(SrcSC) && isGenericCastablePtr(DstSC)) { Register Tmp = MRI->createVirtualRegister(&SPIRV::IDRegClass); - SPIRVType *GenericPtrTy = GR.getOrCreateSPIRVPointerType( + SPIRVType *GenericPtrTy = GTR.getOrCreateSPIRVPointerType( SrcPtrTy, I, TII, SPIRV::StorageClass::Generic); MachineBasicBlock &BB = *I.getParent(); const DebugLoc &DL = I.getDebugLoc(); bool Success = BuildMI(BB, I, DL, TII.get(SPIRV::OpPtrCastToGeneric)) .addDef(Tmp) - .addUse(GR.getSPIRVTypeID(GenericPtrTy)) + .addUse(GTR.getSPIRVTypeID(GenericPtrTy)) .addUse(SrcPtr) .constrainAllUses(TII, TRI, RBI); return Success && BuildMI(BB, I, DL, TII.get(SPIRV::OpGenericCastToPtr)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .addUse(Tmp) .constrainAllUses(TII, TRI, RBI); } @@ -949,7 +951,7 @@ bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg, MachineBasicBlock &BB = *I.getParent(); return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpBitReverse)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .addUse(I.getOperand(1).getReg()) .constrainAllUses(TII, TRI, RBI); } @@ -977,7 +979,7 @@ bool SPIRVInstructionSelector::selectConstVector(Register ResVReg, auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpConstantComposite)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)); + .addUse(GTR.getSPIRVTypeID(ResType)); for (unsigned i = I.getNumExplicitDefs(); i < I.getNumExplicitOperands(); ++i) MIB.addUse(I.getOperand(i).getReg()); return MIB.constrainAllUses(TII, TRI, RBI); @@ -989,12 +991,12 @@ bool SPIRVInstructionSelector::selectCmp(Register ResVReg, MachineInstr &I) const { Register Cmp0 = I.getOperand(2).getReg(); Register Cmp1 = I.getOperand(3).getReg(); - assert(GR.getSPIRVTypeForVReg(Cmp0)->getOpcode() == - GR.getSPIRVTypeForVReg(Cmp1)->getOpcode() && + assert(GTR.getSPIRVTypeForVReg(Cmp0)->getOpcode() == + GTR.getSPIRVTypeForVReg(Cmp1)->getOpcode() && "CMP operands should have the same type"); return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(CmpOpc)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .addUse(Cmp0) .addUse(Cmp1) .constrainAllUses(TII, TRI, RBI); @@ -1007,9 +1009,9 @@ bool SPIRVInstructionSelector::selectICmp(Register ResVReg, unsigned CmpOpc; Register CmpOperand = I.getOperand(2).getReg(); - if (GR.isScalarOfType(CmpOperand, SPIRV::OpTypePointer)) + if (GTR.isScalarOfType(CmpOperand, SPIRV::OpTypePointer)) CmpOpc = getPtrCmpOpcode(Pred); - else if (GR.isScalarOrVectorOfType(CmpOperand, SPIRV::OpTypeBool)) + else if (GTR.isScalarOrVectorOfType(CmpOperand, SPIRV::OpTypeBool)) CmpOpc = getBoolCmpOpcode(Pred); else CmpOpc = getICmpOpcode(Pred); @@ -1036,25 +1038,25 @@ void SPIRVInstructionSelector::renderImm32(MachineInstrBuilder &MIB, Register SPIRVInstructionSelector::buildI32Constant(uint32_t Val, MachineInstr &I, const SPIRVType *ResType) const { - Type *LLVMTy = IntegerType::get(GR.CurMF->getFunction().getContext(), 32); + Type *LLVMTy = IntegerType::get(GTR.CurMF->getFunction().getContext(), 32); const SPIRVType *SpvI32Ty = - ResType ? ResType : GR.getOrCreateSPIRVIntegerType(32, I, TII); + ResType ? ResType : GTR.getOrCreateSPIRVIntegerType(32, I, TII); // Find a constant in DT or build a new one. auto ConstInt = ConstantInt::get(LLVMTy, Val); - Register NewReg = GR.find(ConstInt, GR.CurMF); + Register NewReg = GTR.find(ConstInt, GTR.CurMF); if (!NewReg.isValid()) { NewReg = MRI->createGenericVirtualRegister(LLT::scalar(32)); - GR.add(ConstInt, GR.CurMF, NewReg); + GTR.add(ConstInt, GTR.CurMF, NewReg); MachineInstr *MI; MachineBasicBlock &BB = *I.getParent(); if (Val == 0) { MI = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull)) .addDef(NewReg) - .addUse(GR.getSPIRVTypeID(SpvI32Ty)); + .addUse(GTR.getSPIRVTypeID(SpvI32Ty)); } else { MI = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantI)) .addDef(NewReg) - .addUse(GR.getSPIRVTypeID(SpvI32Ty)) + .addUse(GTR.getSPIRVTypeID(SpvI32Ty)) .addImm(APInt(32, Val).getZExtValue()); } constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); @@ -1072,19 +1074,19 @@ bool SPIRVInstructionSelector::selectFCmp(Register ResVReg, Register SPIRVInstructionSelector::buildZerosVal(const SPIRVType *ResType, MachineInstr &I) const { if (ResType->getOpcode() == SPIRV::OpTypeVector) - return GR.getOrCreateConsIntVector(0, I, ResType, TII); - return GR.getOrCreateConstInt(0, I, ResType, TII); + return GTR.getOrCreateConsIntVector(0, I, ResType, TII); + return GTR.getOrCreateConstInt(0, I, ResType, TII); } Register SPIRVInstructionSelector::buildOnesVal(bool AllOnes, const SPIRVType *ResType, MachineInstr &I) const { - unsigned BitWidth = GR.getScalarOrVectorBitWidth(ResType); + unsigned BitWidth = GTR.getScalarOrVectorBitWidth(ResType); APInt One = AllOnes ? APInt::getAllOnes(BitWidth) : APInt::getOneBitSet(BitWidth, 0); if (ResType->getOpcode() == SPIRV::OpTypeVector) - return GR.getOrCreateConsIntVector(One.getZExtValue(), I, ResType, TII); - return GR.getOrCreateConstInt(One.getZExtValue(), I, ResType, TII); + return GTR.getOrCreateConsIntVector(One.getZExtValue(), I, ResType, TII); + return GTR.getOrCreateConstInt(One.getZExtValue(), I, ResType, TII); } bool SPIRVInstructionSelector::selectSelect(Register ResVReg, @@ -1095,12 +1097,12 @@ bool SPIRVInstructionSelector::selectSelect(Register ResVReg, Register ZeroReg = buildZerosVal(ResType, I); Register OneReg = buildOnesVal(IsSigned, ResType, I); bool IsScalarBool = - GR.isScalarOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool); + GTR.isScalarOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool); unsigned Opcode = IsScalarBool ? SPIRV::OpSelectSISCond : SPIRV::OpSelectSIVCond; return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .addUse(I.getOperand(1).getReg()) .addUse(OneReg) .addUse(ZeroReg) @@ -1114,12 +1116,12 @@ bool SPIRVInstructionSelector::selectIToF(Register ResVReg, Register SrcReg = I.getOperand(1).getReg(); // We can convert bool value directly to float type without OpConvert*ToF, // however the translator generates OpSelect+OpConvert*ToF, so we do the same. - if (GR.isScalarOrVectorOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool)) { - unsigned BitWidth = GR.getScalarOrVectorBitWidth(ResType); - SPIRVType *TmpType = GR.getOrCreateSPIRVIntegerType(BitWidth, I, TII); + if (GTR.isScalarOrVectorOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool)) { + unsigned BitWidth = GTR.getScalarOrVectorBitWidth(ResType); + SPIRVType *TmpType = GTR.getOrCreateSPIRVIntegerType(BitWidth, I, TII); if (ResType->getOpcode() == SPIRV::OpTypeVector) { const unsigned NumElts = ResType->getOperand(2).getImm(); - TmpType = GR.getOrCreateSPIRVVectorType(TmpType, NumElts, I, TII); + TmpType = GTR.getOrCreateSPIRVVectorType(TmpType, NumElts, I, TII); } SrcReg = MRI->createVirtualRegister(&SPIRV::IDRegClass); selectSelect(SrcReg, TmpType, I, false); @@ -1130,7 +1132,7 @@ bool SPIRVInstructionSelector::selectIToF(Register ResVReg, bool SPIRVInstructionSelector::selectExt(Register ResVReg, const SPIRVType *ResType, MachineInstr &I, bool IsSigned) const { - if (GR.isScalarOrVectorOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool)) + if (GTR.isScalarOrVectorOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool)) return selectSelect(ResVReg, ResType, I, IsSigned); unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert; return selectUnOp(ResVReg, ResType, I, Opcode); @@ -1150,13 +1152,13 @@ bool SPIRVInstructionSelector::selectIntToBool(Register IntReg, MachineBasicBlock &BB = *I.getParent(); BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) .addDef(BitIntReg) - .addUse(GR.getSPIRVTypeID(IntTy)) + .addUse(GTR.getSPIRVTypeID(IntTy)) .addUse(IntReg) .addUse(One) .constrainAllUses(TII, TRI, RBI); return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpINotEqual)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(BoolTy)) + .addUse(GTR.getSPIRVTypeID(BoolTy)) .addUse(BitIntReg) .addUse(Zero) .constrainAllUses(TII, TRI, RBI); @@ -1165,12 +1167,12 @@ bool SPIRVInstructionSelector::selectIntToBool(Register IntReg, bool SPIRVInstructionSelector::selectTrunc(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const { - if (GR.isScalarOrVectorOfType(ResVReg, SPIRV::OpTypeBool)) { + if (GTR.isScalarOrVectorOfType(ResVReg, SPIRV::OpTypeBool)) { Register IntReg = I.getOperand(1).getReg(); - const SPIRVType *ArgType = GR.getSPIRVTypeForVReg(IntReg); + const SPIRVType *ArgType = GTR.getSPIRVTypeForVReg(IntReg); return selectIntToBool(IntReg, ResVReg, I, ArgType, ResType); } - bool IsSigned = GR.isScalarOrVectorSigned(ResType); + bool IsSigned = GTR.isScalarOrVectorSigned(ResType); unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert; return selectUnOp(ResVReg, ResType, I, Opcode); } @@ -1186,11 +1188,11 @@ bool SPIRVInstructionSelector::selectConst(Register ResVReg, Imm.isZero()) return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .constrainAllUses(TII, TRI, RBI); if (TyOpcode == SPIRV::OpTypeInt) { assert(Imm.getBitWidth() <= 64 && "Unsupported integer width!"); - Register Reg = GR.getOrCreateConstInt(Imm.getZExtValue(), I, ResType, TII); + Register Reg = GTR.getOrCreateConstInt(Imm.getZExtValue(), I, ResType, TII); if (Reg == ResVReg) return true; return BuildMI(BB, I, I.getDebugLoc(), TII.get(TargetOpcode::COPY)) @@ -1200,7 +1202,7 @@ bool SPIRVInstructionSelector::selectConst(Register ResVReg, } auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantI)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)); + .addUse(GTR.getSPIRVTypeID(ResType)); // <=32-bit integers should be caught by the sdag pattern. assert(Imm.getBitWidth() > 32); addNumImm(Imm, MIB); @@ -1212,7 +1214,7 @@ bool SPIRVInstructionSelector::selectOpUndef(Register ResVReg, MachineInstr &I) const { return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpUndef)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .constrainAllUses(TII, TRI, RBI); } @@ -1239,7 +1241,7 @@ bool SPIRVInstructionSelector::selectInsertVal(Register ResVReg, MachineBasicBlock &BB = *I.getParent(); auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeInsert)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) // object to insert .addUse(I.getOperand(3).getReg()) // composite to insert into @@ -1255,7 +1257,7 @@ bool SPIRVInstructionSelector::selectExtractVal(Register ResVReg, MachineBasicBlock &BB = *I.getParent(); auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .addUse(I.getOperand(2).getReg()); for (unsigned i = 3; i < I.getNumOperands(); i++) MIB.addImm(foldImm(I.getOperand(i), MRI)); @@ -1270,7 +1272,7 @@ bool SPIRVInstructionSelector::selectInsertElt(Register ResVReg, MachineBasicBlock &BB = *I.getParent(); return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorInsertDynamic)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .addUse(I.getOperand(2).getReg()) .addUse(I.getOperand(3).getReg()) .addUse(I.getOperand(4).getReg()) @@ -1285,7 +1287,7 @@ bool SPIRVInstructionSelector::selectExtractElt(Register ResVReg, MachineBasicBlock &BB = *I.getParent(); return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorExtractDynamic)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .addUse(I.getOperand(2).getReg()) .addUse(I.getOperand(3).getReg()) .constrainAllUses(TII, TRI, RBI); @@ -1301,7 +1303,7 @@ bool SPIRVInstructionSelector::selectGEP(Register ResVReg, : SPIRV::OpPtrAccessChain; auto Res = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) // Object to get a pointer to. .addUse(I.getOperand(3).getReg()); // Adding indices. @@ -1341,7 +1343,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, case Intrinsic::spv_undef: { auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpUndef)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)); + .addUse(GTR.getSPIRVTypeID(ResType)); return MIB.constrainAllUses(TII, TRI, RBI); } case Intrinsic::spv_const_composite: { @@ -1351,7 +1353,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, IsNull ? SPIRV::OpConstantNull : SPIRV::OpConstantComposite; auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)); + .addUse(GTR.getSPIRVTypeID(ResType)); // skip type MD node we already used when generated assign.type for this if (!IsNull) { for (unsigned i = I.getNumExplicitDefs() + 1; @@ -1402,7 +1404,7 @@ bool SPIRVInstructionSelector::selectFrameIndex(Register ResVReg, MachineInstr &I) const { return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpVariable)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .addImm(static_cast(SPIRV::StorageClass::Function)) .constrainAllUses(TII, TRI, RBI); } @@ -1458,7 +1460,7 @@ bool SPIRVInstructionSelector::selectPhi(Register ResVReg, MachineInstr &I) const { auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpPhi)) .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)); + .addUse(GTR.getSPIRVTypeID(ResType)); const unsigned NumOps = I.getNumOperands(); for (unsigned i = 1; i < NumOps; i += 2) { MIB.addUse(I.getOperand(i + 0).getReg()); @@ -1472,7 +1474,7 @@ bool SPIRVInstructionSelector::selectGlobalValue( // FIXME: don't use MachineIRBuilder here, replace it with BuildMI. MachineIRBuilder MIRBuilder(I); const GlobalValue *GV = I.getOperand(1).getGlobal(); - SPIRVType *ResType = GR.getOrCreateSPIRVType( + SPIRVType *ResType = GTR.getOrCreateSPIRVType( GV->getType(), MIRBuilder, SPIRV::AccessQualifier::ReadWrite, false); std::string GlobalIdent = GV->getGlobalIdentifier(); @@ -1483,15 +1485,15 @@ bool SPIRVInstructionSelector::selectGlobalValue( if (isa(GV)) { const Constant *ConstVal = GV; MachineBasicBlock &BB = *I.getParent(); - Register NewReg = GR.find(ConstVal, GR.CurMF); + Register NewReg = GTR.find(ConstVal, GTR.CurMF); if (!NewReg.isValid()) { - SPIRVType *SpvBaseTy = GR.getOrCreateSPIRVIntegerType(8, I, TII); - ResType = GR.getOrCreateSPIRVPointerType(SpvBaseTy, I, TII); + SPIRVType *SpvBaseTy = GTR.getOrCreateSPIRVIntegerType(8, I, TII); + ResType = GTR.getOrCreateSPIRVPointerType(SpvBaseTy, I, TII); Register NewReg = ResVReg; - GR.add(ConstVal, GR.CurMF, NewReg); + GTR.add(ConstVal, GTR.CurMF, NewReg); return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull)) .addDef(NewReg) - .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GTR.getSPIRVTypeID(ResType)) .constrainAllUses(TII, TRI, RBI); } assert(NewReg != ResVReg); @@ -1520,9 +1522,9 @@ bool SPIRVInstructionSelector::selectGlobalValue( ? SPIRV::LinkageType::Import : SPIRV::LinkageType::Export; - Register Reg = GR.buildGlobalVariable(ResVReg, ResType, GlobalIdent, GV, - Storage, Init, GlobalVar->isConstant(), - HasLnkTy, LnkType, MIRBuilder, true); + Register Reg = GTR.buildGlobalVariable(ResVReg, ResType, GlobalIdent, GV, + Storage, Init, GlobalVar->isConstant(), + HasLnkTy, LnkType, MIRBuilder, true); return Reg.isValid(); } diff --git a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp index b0028f8c80a4..bfbcd8b96c84 100644 --- a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp @@ -12,7 +12,7 @@ #include "SPIRVLegalizerInfo.h" #include "SPIRV.h" -#include "SPIRVGlobalRegistry.h" +#include "Registries/SPIRVGlobalTypeRegistry.h" #include "SPIRVSubtarget.h" #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" @@ -58,7 +58,7 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) { using namespace TargetOpcode; this->ST = &ST; - GR = ST.getSPIRVGlobalRegistry(); + GTR = ST.getSPIRVGlobalTypeRegistry(); const LLT s1 = LLT::scalar(1); const LLT s8 = LLT::scalar(8); @@ -277,9 +277,9 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) { static Register convertPtrToInt(Register Reg, LLT ConvTy, SPIRVType *SpirvType, LegalizerHelper &Helper, MachineRegisterInfo &MRI, - SPIRVGlobalRegistry *GR) { + SPIRVGlobalTypeRegistry *GTR) { Register ConvReg = MRI.createGenericVirtualRegister(ConvTy); - GR->assignSPIRVTypeToVReg(SpirvType, ConvReg, Helper.MIRBuilder.getMF()); + GTR->assignSPIRVTypeToVReg(SpirvType, ConvReg, Helper.MIRBuilder.getMF()); Helper.MIRBuilder.buildInstr(TargetOpcode::G_PTRTOINT) .addDef(ConvReg) .addUse(Reg); @@ -292,7 +292,7 @@ bool SPIRVLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineRegisterInfo &MRI = MI.getMF()->getRegInfo(); if (!isTypeFoldingSupported(Opc)) { assert(Opc == TargetOpcode::G_ICMP); - assert(GR->getSPIRVTypeForVReg(MI.getOperand(0).getReg())); + assert(GTR->getSPIRVTypeForVReg(MI.getOperand(0).getReg())); auto &Op0 = MI.getOperand(2); auto &Op1 = MI.getOperand(3); Register Reg0 = Op0.getReg(); @@ -305,9 +305,9 @@ bool SPIRVLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, LLT ConvT = LLT::scalar(ST->getPointerSize()); Type *LLVMTy = IntegerType::get(MI.getMF()->getFunction().getContext(), ST->getPointerSize()); - SPIRVType *SpirvTy = GR->getOrCreateSPIRVType(LLVMTy, Helper.MIRBuilder); - Op0.setReg(convertPtrToInt(Reg0, ConvT, SpirvTy, Helper, MRI, GR)); - Op1.setReg(convertPtrToInt(Reg1, ConvT, SpirvTy, Helper, MRI, GR)); + SPIRVType *SpirvTy = GTR->getOrCreateSPIRVType(LLVMTy, Helper.MIRBuilder); + Op0.setReg(convertPtrToInt(Reg0, ConvT, SpirvTy, Helper, MRI, GTR)); + Op1.setReg(convertPtrToInt(Reg1, ConvT, SpirvTy, Helper, MRI, GTR)); } return true; } diff --git a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.h b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.h index 2541ff29edb0..b9cd427042ed 100644 --- a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.h +++ b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.h @@ -13,7 +13,7 @@ #ifndef LLVM_LIB_TARGET_SPIRV_SPIRVMACHINELEGALIZER_H #define LLVM_LIB_TARGET_SPIRV_SPIRVMACHINELEGALIZER_H -#include "SPIRVGlobalRegistry.h" +#include "Registries/SPIRVGlobalTypeRegistry.h" #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" bool isTypeFoldingSupported(unsigned Opcode); @@ -26,7 +26,7 @@ class SPIRVSubtarget; // This class provides the information for legalizing SPIR-V instructions. class SPIRVLegalizerInfo : public LegalizerInfo { const SPIRVSubtarget *ST; - SPIRVGlobalRegistry *GR; + SPIRVGlobalTypeRegistry *GTR; public: bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override; diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp index 22746788607b..05082a17e86f 100644 --- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp @@ -219,7 +219,7 @@ void SPIRVModuleAnalysis::collectGlobalEntities( void SPIRVModuleAnalysis::processDefInstrs(const Module &M) { std::vector DepsGraph; - GR->buildDepsGraph(DepsGraph, SPVDumpDeps ? MMI : nullptr); + GTR->buildDepsGraph(DepsGraph, SPVDumpDeps ? MMI : nullptr); collectGlobalEntities( DepsGraph, SPIRV::MB_TypeConstVars, @@ -968,7 +968,7 @@ bool SPIRVModuleAnalysis::runOnModule(Module &M) { SPIRVTargetMachine &TM = getAnalysis().getTM(); ST = TM.getSubtargetImpl(); - GR = ST->getSPIRVGlobalRegistry(); + GTR = ST->getSPIRVGlobalTypeRegistry(); TII = ST->getInstrInfo(); MMI = &getAnalysis().getMMI(); diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h index abb6797c5218..396ad57f260e 100644 --- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h +++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h @@ -15,7 +15,7 @@ #define LLVM_LIB_TARGET_SPIRV_SPIRVMODULEANALYSIS_H #include "MCTargetDesc/SPIRVBaseInfo.h" -#include "SPIRVGlobalRegistry.h" +#include "Registries/SPIRVGlobalTypeRegistry.h" #include "SPIRVUtils.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallSet.h" @@ -213,7 +213,7 @@ struct SPIRVModuleAnalysis : public ModulePass { void numberRegistersGlobally(const Module &M); const SPIRVSubtarget *ST; - SPIRVGlobalRegistry *GR; + SPIRVGlobalTypeRegistry *GTR; const SPIRVInstrInfo *TII; MachineModuleInfo *MMI; }; diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp index 1e664ca6cfcd..9327c8ecbdd8 100644 --- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp @@ -38,7 +38,8 @@ class SPIRVPreLegalizer : public MachineFunctionPass { }; } // namespace -static void addConstantsToTrack(MachineFunction &MF, SPIRVGlobalRegistry *GR) { +static void addConstantsToTrack(MachineFunction &MF, + SPIRVGlobalTypeRegistry *GTR) { MachineRegisterInfo &MRI = MF.getRegInfo(); DenseMap RegsAlreadyAddedToDT; SmallVector ToErase, ToEraseComposites; @@ -52,23 +53,23 @@ static void addConstantsToTrack(MachineFunction &MF, SPIRVGlobalRegistry *GR) { MI.getOperand(3).getMetadata()->getOperand(0)) ->getValue()); if (auto *GV = dyn_cast(Const)) { - Register Reg = GR->find(GV, &MF); + Register Reg = GTR->find(GV, &MF); if (!Reg.isValid()) - GR->add(GV, &MF, MI.getOperand(2).getReg()); + GTR->add(GV, &MF, MI.getOperand(2).getReg()); else RegsAlreadyAddedToDT[&MI] = Reg; } else { - Register Reg = GR->find(Const, &MF); + Register Reg = GTR->find(Const, &MF); if (!Reg.isValid()) { if (auto *ConstVec = dyn_cast(Const)) { auto *BuildVec = MRI.getVRegDef(MI.getOperand(2).getReg()); assert(BuildVec && BuildVec->getOpcode() == TargetOpcode::G_BUILD_VECTOR); for (unsigned i = 0; i < ConstVec->getNumElements(); ++i) - GR->add(ConstVec->getElementAsConstant(i), &MF, - BuildVec->getOperand(1 + i).getReg()); + GTR->add(ConstVec->getElementAsConstant(i), &MF, + BuildVec->getOperand(1 + i).getReg()); } - GR->add(Const, &MF, MI.getOperand(2).getReg()); + GTR->add(Const, &MF, MI.getOperand(2).getReg()); } else { RegsAlreadyAddedToDT[&MI] = Reg; // This MI is unused and will be removed. If the MI uses @@ -117,7 +118,7 @@ static void foldConstantsIntoIntrinsics(MachineFunction &MF) { MI->eraseFromParent(); } -static void insertBitcasts(MachineFunction &MF, SPIRVGlobalRegistry *GR, +static void insertBitcasts(MachineFunction &MF, SPIRVGlobalTypeRegistry *GTR, MachineIRBuilder MIB) { SmallVector ToErase; for (MachineBasicBlock &MBB : MF) { @@ -142,26 +143,27 @@ static void insertBitcasts(MachineFunction &MF, SPIRVGlobalRegistry *GR, // // Set SPIRVType for GV, propagate it from GV to other instructions, // also set register classes. -static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR, +static SPIRVType *propagateSPIRVType(MachineInstr *MI, + SPIRVGlobalTypeRegistry *GTR, MachineRegisterInfo &MRI, MachineIRBuilder &MIB) { SPIRVType *SpirvTy = nullptr; assert(MI && "Machine instr is expected"); if (MI->getOperand(0).isReg()) { Register Reg = MI->getOperand(0).getReg(); - SpirvTy = GR->getSPIRVTypeForVReg(Reg); + SpirvTy = GTR->getSPIRVTypeForVReg(Reg); if (!SpirvTy) { switch (MI->getOpcode()) { case TargetOpcode::G_CONSTANT: { MIB.setInsertPt(*MI->getParent(), MI); Type *Ty = MI->getOperand(1).getCImm()->getType(); - SpirvTy = GR->getOrCreateSPIRVType(Ty, MIB); + SpirvTy = GTR->getOrCreateSPIRVType(Ty, MIB); break; } case TargetOpcode::G_GLOBAL_VALUE: { MIB.setInsertPt(*MI->getParent(), MI); Type *Ty = MI->getOperand(1).getGlobal()->getType(); - SpirvTy = GR->getOrCreateSPIRVType(Ty, MIB); + SpirvTy = GTR->getOrCreateSPIRVType(Ty, MIB); break; } case TargetOpcode::G_TRUNC: @@ -171,14 +173,14 @@ static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR, MachineOperand &Op = MI->getOperand(1); MachineInstr *Def = Op.isReg() ? MRI.getVRegDef(Op.getReg()) : nullptr; if (Def) - SpirvTy = propagateSPIRVType(Def, GR, MRI, MIB); + SpirvTy = propagateSPIRVType(Def, GTR, MRI, MIB); break; } default: break; } if (SpirvTy) - GR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF()); + GTR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF()); if (!MRI.getRegClassOrNull(Reg)) MRI.setRegClass(Reg, &SPIRV::IDRegClass); } @@ -193,7 +195,7 @@ static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR, // TODO: maybe move to SPIRVUtils. namespace llvm { Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy, - SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB, + SPIRVGlobalTypeRegistry *GTR, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) { MachineInstr *Def = MRI.getVRegDef(Reg); assert((Ty || SpirvTy) && "Either LLVM or SPIRV type is expected."); @@ -203,18 +205,18 @@ Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy, Register NewReg = MRI.createGenericVirtualRegister(MRI.getType(Reg)); if (auto *RC = MRI.getRegClassOrNull(Reg)) MRI.setRegClass(NewReg, RC); - SpirvTy = SpirvTy ? SpirvTy : GR->getOrCreateSPIRVType(Ty, MIB); - GR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF()); + SpirvTy = SpirvTy ? SpirvTy : GTR->getOrCreateSPIRVType(Ty, MIB); + GTR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF()); // This is to make it convenient for Legalizer to get the SPIRVType // when processing the actual MI (i.e. not pseudo one). - GR->assignSPIRVTypeToVReg(SpirvTy, NewReg, MIB.getMF()); + GTR->assignSPIRVTypeToVReg(SpirvTy, NewReg, MIB.getMF()); // Copy MIFlags from Def to ASSIGN_TYPE instruction. It's required to keep // the flags after instruction selection. const uint16_t Flags = Def->getFlags(); MIB.buildInstr(SPIRV::ASSIGN_TYPE) .addDef(Reg) .addUse(NewReg) - .addUse(GR->getSPIRVTypeID(SpirvTy)) + .addUse(GTR->getSPIRVTypeID(SpirvTy)) .setMIFlags(Flags); Def->getOperand(0).setReg(NewReg); MRI.setRegClass(Reg, &SPIRV::ANYIDRegClass); @@ -222,7 +224,8 @@ Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy, } } // namespace llvm -static void generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR, +static void generateAssignInstrs(MachineFunction &MF, + SPIRVGlobalTypeRegistry *GTR, MachineIRBuilder MIB) { MachineRegisterInfo &MRI = MF.getRegInfo(); SmallVector ToErase; @@ -243,7 +246,7 @@ static void generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR, assert(Def && "Expecting an instruction that defines the register"); // G_GLOBAL_VALUE already has type info. if (Def->getOpcode() != TargetOpcode::G_GLOBAL_VALUE) - insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MF.getRegInfo()); + insertAssignInstr(Reg, Ty, nullptr, GTR, MIB, MF.getRegInfo()); ToErase.push_back(&MI); } else if (MI.getOpcode() == TargetOpcode::G_CONSTANT || MI.getOpcode() == TargetOpcode::G_FCONSTANT || @@ -281,12 +284,12 @@ static void generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR, MI.getNumExplicitOperands() - MI.getNumExplicitDefs(); Ty = VectorType::get(ElemTy, NumElts, false); } - insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MRI); + insertAssignInstr(Reg, Ty, nullptr, GTR, MIB, MRI); } else if (MI.getOpcode() == TargetOpcode::G_TRUNC || MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE || MI.getOpcode() == TargetOpcode::COPY || MI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST) { - propagateSPIRVType(&MI, GR, MRI, MIB); + propagateSPIRVType(&MI, GTR, MRI, MIB); } if (MII == Begin) @@ -301,14 +304,14 @@ static void generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR, static std::pair createNewIdReg(Register ValReg, unsigned Opcode, MachineRegisterInfo &MRI, - const SPIRVGlobalRegistry &GR) { + const SPIRVGlobalTypeRegistry >R) { LLT NewT = LLT::scalar(32); - SPIRVType *SpvType = GR.getSPIRVTypeForVReg(ValReg); + SPIRVType *SpvType = GTR.getSPIRVTypeForVReg(ValReg); assert(SpvType && "VReg is expected to have SPIRV type"); bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat; bool IsVectorFloat = SpvType->getOpcode() == SPIRV::OpTypeVector && - GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())->getOpcode() == + GTR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())->getOpcode() == SPIRV::OpTypeFloat; IsFloat |= IsVectorFloat; auto GetIdOp = IsFloat ? SPIRV::GET_fID : SPIRV::GET_ID; @@ -328,12 +331,13 @@ createNewIdReg(Register ValReg, unsigned Opcode, MachineRegisterInfo &MRI, } static void processInstr(MachineInstr &MI, MachineIRBuilder &MIB, - MachineRegisterInfo &MRI, SPIRVGlobalRegistry *GR) { + MachineRegisterInfo &MRI, + SPIRVGlobalTypeRegistry *GTR) { unsigned Opc = MI.getOpcode(); assert(MI.getNumDefs() > 0 && MRI.hasOneUse(MI.getOperand(0).getReg())); MachineInstr &AssignTypeInst = *(MRI.use_instr_begin(MI.getOperand(0).getReg())); - auto NewReg = createNewIdReg(MI.getOperand(0).getReg(), Opc, MRI, *GR).first; + auto NewReg = createNewIdReg(MI.getOperand(0).getReg(), Opc, MRI, *GTR).first; AssignTypeInst.getOperand(1).setReg(NewReg); MI.getOperand(0).setReg(NewReg); MIB.setInsertPt(*MI.getParent(), @@ -342,7 +346,7 @@ static void processInstr(MachineInstr &MI, MachineIRBuilder &MIB, for (auto &Op : MI.operands()) { if (!Op.isReg() || Op.isDef()) continue; - auto IdOpInfo = createNewIdReg(Op.getReg(), Opc, MRI, *GR); + auto IdOpInfo = createNewIdReg(Op.getReg(), Opc, MRI, *GTR); MIB.buildInstr(IdOpInfo.second).addDef(IdOpInfo.first).addUse(Op.getReg()); Op.setReg(IdOpInfo.first); } @@ -352,13 +356,13 @@ static void processInstr(MachineInstr &MI, MachineIRBuilder &MIB, extern bool isTypeFoldingSupported(unsigned Opcode); static void processInstrsWithTypeFolding(MachineFunction &MF, - SPIRVGlobalRegistry *GR, + SPIRVGlobalTypeRegistry *GTR, MachineIRBuilder MIB) { MachineRegisterInfo &MRI = MF.getRegInfo(); for (MachineBasicBlock &MBB : MF) { for (MachineInstr &MI : MBB) { if (isTypeFoldingSupported(MI.getOpcode())) - processInstr(MI, MIB, MRI, GR); + processInstr(MI, MIB, MRI, GTR); } } for (MachineBasicBlock &MBB : MF) { @@ -387,7 +391,7 @@ static void processInstrsWithTypeFolding(MachineFunction &MF, } } -static void processSwitches(MachineFunction &MF, SPIRVGlobalRegistry *GR, +static void processSwitches(MachineFunction &MF, SPIRVGlobalTypeRegistry *GTR, MachineIRBuilder MIB) { // Before IRTranslator pass, calls to spv_switch intrinsic are inserted before // each switch instruction. IRTranslator lowers switches to G_ICMP + G_BRCOND @@ -571,15 +575,15 @@ static void processSwitches(MachineFunction &MF, SPIRVGlobalRegistry *GR, bool SPIRVPreLegalizer::runOnMachineFunction(MachineFunction &MF) { // Initialize the type registry. const SPIRVSubtarget &ST = MF.getSubtarget(); - SPIRVGlobalRegistry *GR = ST.getSPIRVGlobalRegistry(); - GR->setCurrentFunc(MF); + SPIRVGlobalTypeRegistry *GTR = ST.getSPIRVGlobalTypeRegistry(); + GTR->setCurrentFunc(MF); MachineIRBuilder MIB(MF); - addConstantsToTrack(MF, GR); + addConstantsToTrack(MF, GTR); foldConstantsIntoIntrinsics(MF); - insertBitcasts(MF, GR, MIB); - generateAssignInstrs(MF, GR, MIB); - processSwitches(MF, GR, MIB); - processInstrsWithTypeFolding(MF, GR, MIB); + insertBitcasts(MF, GTR, MIB); + generateAssignInstrs(MF, GTR, MIB); + processSwitches(MF, GTR, MIB); + processInstrsWithTypeFolding(MF, GTR, MIB); return true; } diff --git a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp index 0f047b09c521..a177fb2bda76 100644 --- a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp @@ -12,7 +12,7 @@ #include "SPIRVSubtarget.h" #include "SPIRV.h" -#include "SPIRVGlobalRegistry.h" +#include "Registries/SPIRVGlobalTypeRegistry.h" #include "SPIRVLegalizerInfo.h" #include "SPIRVRegisterBankInfo.h" #include "SPIRVTargetMachine.h" @@ -50,8 +50,8 @@ SPIRVSubtarget::SPIRVSubtarget(const Triple &TT, const std::string &CPU, initAvailableExtensions(); initAvailableExtInstSets(); - GR = std::make_unique(PointerSize); - CallLoweringInfo = std::make_unique(TLInfo, GR.get()); + GTR = std::make_unique(PointerSize); + CallLoweringInfo = std::make_unique(TLInfo, GTR.get()); Legalizer = std::make_unique(*this); RegBankInfo = std::make_unique(); InstSelector.reset( diff --git a/llvm/lib/Target/SPIRV/SPIRVSubtarget.h b/llvm/lib/Target/SPIRV/SPIRVSubtarget.h index dd19a1d0a9bb..cf72da858f7f 100644 --- a/llvm/lib/Target/SPIRV/SPIRVSubtarget.h +++ b/llvm/lib/Target/SPIRV/SPIRVSubtarget.h @@ -40,7 +40,7 @@ class SPIRVSubtarget : public SPIRVGenSubtargetInfo { SmallSet AvailableExtensions; SmallSet AvailableExtInstSets; - std::unique_ptr GR; + std::unique_ptr GTR; SPIRVInstrInfo InstrInfo; SPIRVFrameLowering FrameLowering; @@ -82,7 +82,9 @@ class SPIRVSubtarget : public SPIRVGenSubtargetInfo { bool canUseExtension(SPIRV::Extension::Extension E) const; bool canUseExtInstSet(SPIRV::InstructionSet::InstructionSet E) const; - SPIRVGlobalRegistry *getSPIRVGlobalRegistry() const { return GR.get(); } + SPIRVGlobalTypeRegistry *getSPIRVGlobalTypeRegistry() const { + return GTR.get(); + } const CallLowering *getCallLowering() const override { return CallLoweringInfo.get(); diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp index 6721c60834bd..804a01379f17 100644 --- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp @@ -13,7 +13,7 @@ #include "SPIRVTargetMachine.h" #include "SPIRV.h" #include "SPIRVCallLowering.h" -#include "SPIRVGlobalRegistry.h" +#include "Registries/SPIRVGlobalTypeRegistry.h" #include "SPIRVLegalizerInfo.h" #include "SPIRVTargetObjectFile.h" #include "SPIRVTargetTransformInfo.h" From d1a31fa5dc115110e0616d77587d09ad78c37c92 Mon Sep 17 00:00:00 2001 From: Michal Paszkowski Date: Mon, 10 Apr 2023 02:22:51 +0200 Subject: [PATCH 3/5] [SPIR-V] Mark GlobalTypeRegistry find/add args as const --- .../SPIRV/Registries/SPIRVGlobalTypeRegistry.h | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.h b/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.h index 61564e474ba2..fed5d92033ef 100644 --- a/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.h +++ b/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.h @@ -68,31 +68,32 @@ class SPIRVGlobalTypeRegistry { MachineFunction *CurMF; - void add(const Constant *C, MachineFunction *MF, Register R) { + void add(const Constant *C, const MachineFunction *MF, const Register R) { DT.add(C, MF, R); } - void add(const GlobalVariable *GV, MachineFunction *MF, Register R) { + void add(const GlobalVariable *GV, const MachineFunction *MF, + const Register R) { DT.add(GV, MF, R); } - void add(const Function *F, MachineFunction *MF, Register R) { + void add(const Function *F, const MachineFunction *MF, const Register R) { DT.add(F, MF, R); } - void add(const Argument *Arg, MachineFunction *MF, Register R) { + void add(const Argument *Arg, const MachineFunction *MF, const Register R) { DT.add(Arg, MF, R); } - Register find(const Constant *C, MachineFunction *MF) { + Register find(const Constant *C, const MachineFunction *MF) { return DT.find(C, MF); } - Register find(const GlobalVariable *GV, MachineFunction *MF) { + Register find(const GlobalVariable *GV, const MachineFunction *MF) { return DT.find(GV, MF); } - Register find(const Function *F, MachineFunction *MF) { + Register find(const Function *F, const MachineFunction *MF) { return DT.find(F, MF); } From ed5372c87266abc428054a80438d326185671239 Mon Sep 17 00:00:00 2001 From: Michal Paszkowski Date: Mon, 10 Apr 2023 03:20:07 +0200 Subject: [PATCH 4/5] [SPIR-V] Add SPIRVGlobalInstrRegistry, don't emit OpEntryPoint in MF --- .../Registries/SPIRVGlobalInstrRegistry.h | 60 +++++++++++++++++++ llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp | 13 +++- llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp | 11 ++-- llvm/lib/Target/SPIRV/SPIRVCallLowering.h | 7 ++- llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 5 +- llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h | 3 +- llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp | 4 +- llvm/lib/Target/SPIRV/SPIRVSubtarget.h | 7 +++ 8 files changed, 95 insertions(+), 15 deletions(-) create mode 100644 llvm/lib/Target/SPIRV/Registries/SPIRVGlobalInstrRegistry.h diff --git a/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalInstrRegistry.h b/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalInstrRegistry.h new file mode 100644 index 000000000000..dca188378733 --- /dev/null +++ b/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalInstrRegistry.h @@ -0,0 +1,60 @@ +//===-- SPIRVGlobalInstrRegistry.h - SPIR-V Global Instr Registry -*- C++ +//-*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===------------------------------------------------------------------------===// +// +// The SPIRVGlobalInstrRegistry class is used to collect and contain information +// required for emitting SPIR-V global instructions (instructions which do not +// belong to any function and are emittied on a module level). +// +//===------------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVGLOBALINSTRREGISTRY_H +#define LLVM_LIB_TARGET_SPIRV_SPIRVGLOBALINSTRREGISTRY_H + +#include "MCTargetDesc/SPIRVBaseInfo.h" + +#include "llvm/ADT/SmallVector.h" +#include "llvm/IR/Function.h" + +namespace llvm { +namespace SPIRV { +/// Struct representing a global OpEntryPoint instruction for later printing. +struct OpEntryPointInst { + const SPIRV::ExecutionModel::ExecutionModel ExecModel; + const Function *const EntryFunction; + + OpEntryPointInst(const SPIRV::ExecutionModel::ExecutionModel ExecModel, + const Function *const EntryFunction) + : ExecModel(ExecModel), EntryFunction(EntryFunction) {} + OpEntryPointInst &operator=(const OpEntryPointInst &) = delete; +}; +} // namespace SPIRV + +/// SPIRVGlobalInstrRegistry collects and stores information required for +/// emitting SPIR-V global instructions. +class SPIRVGlobalInstrRegistry { +private: + SmallVector OpEntryPoints; + +public: + SPIRVGlobalInstrRegistry() {} + + /// Declare a new SPIR-V entry point. + void addEntryPoint(const SPIRV::ExecutionModel::ExecutionModel ExecModel, + const Function *const EntryFunction) { + OpEntryPoints.push_back(SPIRV::OpEntryPointInst(ExecModel, EntryFunction)); + } + + /// Get all already declared SPIR-V entry points. + const SmallVector &getAllEntryPoints() const { + return OpEntryPoints; + } +}; + +} // namespace llvm +#endif // LLVM_LIB_TARGET_SPIRV_SPIRVGLOBALINSTRREGISTRY_H diff --git a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp index d07c0bcdf9af..fe2322c8f221 100644 --- a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp @@ -84,6 +84,7 @@ class SPIRVAsmPrinter : public AsmPrinter { void getAnalysisUsage(AnalysisUsage &AU) const override; SPIRV::ModuleAnalysisInfo *MAI; + SPIRVGlobalInstrRegistry *GIR; }; } // namespace @@ -308,10 +309,15 @@ void SPIRVAsmPrinter::outputEntryPoints() { } // Output OpEntryPoints adding interface args to all of them. - for (MachineInstr *MI : MAI->getMSInstrs(SPIRV::MB_EntryPoints)) { - SPIRVMCInstLower MCInstLowering; + for (const SPIRV::OpEntryPointInst &EP : GIR->getAllEntryPoints()) { MCInst TmpInst; - MCInstLowering.lower(MI, TmpInst, MAI); + TmpInst.setOpcode(SPIRV::OpEntryPoint); + TmpInst.addOperand( + MCOperand::createImm(static_cast(EP.ExecModel))); + Register EntryFuncReg = MAI->getFuncReg(EP.EntryFunction); + TmpInst.addOperand(MCOperand::createReg(EntryFuncReg)); + addStringImm(EP.EntryFunction->getName(), TmpInst); + for (Register Reg : InterfaceIDs) { assert(Reg.isValid()); TmpInst.addOperand(MCOperand::createReg(Reg)); @@ -500,6 +506,7 @@ void SPIRVAsmPrinter::outputModuleSections() { ST = static_cast(TM).getSubtargetImpl(); TII = ST->getInstrInfo(); MAI = &SPIRVModuleAnalysis::MAI; + GIR = ST->getSPIRVGlobalInstrRegistry(); assert(ST && TII && MAI && M && "Module analysis is required"); // Output instructions according to the Logical Layout of a Module: // 1,2. All OpCapability instructions, then optional OpExtension instructions. diff --git a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp index 8e6af77c21a6..8348893e013a 100644 --- a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp @@ -16,6 +16,7 @@ #include "SPIRV.h" #include "SPIRVBuiltins.h" #include "Registries/SPIRVGlobalTypeRegistry.h" +#include "Registries/SPIRVGlobalInstrRegistry.h" #include "SPIRVISelLowering.h" #include "SPIRVRegisterInfo.h" #include "SPIRVSubtarget.h" @@ -26,8 +27,9 @@ using namespace llvm; SPIRVCallLowering::SPIRVCallLowering(const SPIRVTargetLowering &TLI, - SPIRVGlobalTypeRegistry *GTR) - : CallLowering(&TLI), GTR(GTR) {} + SPIRVGlobalTypeRegistry *GTR, + SPIRVGlobalInstrRegistry *GIR) + : CallLowering(&TLI), GTR(GTR), GIR(GIR) {} bool SPIRVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef VRegs, @@ -339,10 +341,7 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, // Handle entry points and function linkage. if (F.getCallingConv() == CallingConv::SPIR_KERNEL) { - auto MIB = MIRBuilder.buildInstr(SPIRV::OpEntryPoint) - .addImm(static_cast(SPIRV::ExecutionModel::Kernel)) - .addUse(FuncVReg); - addStringImm(F.getName(), MIB); + GIR->addEntryPoint(SPIRV::ExecutionModel::Kernel, &F); } else if (F.getLinkage() == GlobalValue::LinkageTypes::ExternalLinkage || F.getLinkage() == GlobalValue::LinkOnceODRLinkage) { auto LnkTy = F.isDeclaration() ? SPIRV::LinkageType::Import diff --git a/llvm/lib/Target/SPIRV/SPIRVCallLowering.h b/llvm/lib/Target/SPIRV/SPIRVCallLowering.h index 536139c38edc..d70e28bf5754 100644 --- a/llvm/lib/Target/SPIRV/SPIRVCallLowering.h +++ b/llvm/lib/Target/SPIRV/SPIRVCallLowering.h @@ -14,6 +14,7 @@ #define LLVM_LIB_TARGET_SPIRV_SPIRVCALLLOWERING_H #include "Registries/SPIRVGlobalTypeRegistry.h" +#include "Registries/SPIRVGlobalInstrRegistry.h" #include "llvm/CodeGen/GlobalISel/CallLowering.h" namespace llvm { @@ -26,9 +27,13 @@ class SPIRVCallLowering : public CallLowering { // Used to create and assign function, argument, and return type information. SPIRVGlobalTypeRegistry *GTR; + // Used to create global instructions which do not belong to any function. + SPIRVGlobalInstrRegistry *GIR; + public: SPIRVCallLowering(const SPIRVTargetLowering &TLI, - SPIRVGlobalTypeRegistry *GTR); + SPIRVGlobalTypeRegistry *GTR, + SPIRVGlobalInstrRegistry *GIR); // Built OpReturn or OpReturnValue. bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val, diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp index 05082a17e86f..f7535760a62c 100644 --- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp @@ -338,8 +338,6 @@ void SPIRVModuleAnalysis::processOtherInstrs(const Module &M) { const unsigned OpCode = MI.getOpcode(); if (OpCode == SPIRV::OpName || OpCode == SPIRV::OpMemberName) { collectOtherInstr(MI, MAI, SPIRV::MB_DebugNames); - } else if (OpCode == SPIRV::OpEntryPoint) { - collectOtherInstr(MI, MAI, SPIRV::MB_EntryPoints); } else if (TII->isDecorationInstr(MI)) { collectOtherInstr(MI, MAI, SPIRV::MB_Annotations); collectFuncNames(MI, &*F); @@ -969,6 +967,7 @@ bool SPIRVModuleAnalysis::runOnModule(Module &M) { getAnalysis().getTM(); ST = TM.getSubtargetImpl(); GTR = ST->getSPIRVGlobalTypeRegistry(); + GIR = ST->getSPIRVGlobalInstrRegistry(); TII = ST->getInstrInfo(); MMI = &getAnalysis().getMMI(); @@ -990,7 +989,7 @@ bool SPIRVModuleAnalysis::runOnModule(Module &M) { processOtherInstrs(M); // If there are no entry points, we need the Linkage capability. - if (MAI.MS[SPIRV::MB_EntryPoints].empty()) + if (GIR->getAllEntryPoints().empty()) MAI.Reqs.addCapability(SPIRV::Capability::Linkage); return false; diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h index 396ad57f260e..6027a1dec429 100644 --- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h +++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h @@ -16,6 +16,7 @@ #include "MCTargetDesc/SPIRVBaseInfo.h" #include "Registries/SPIRVGlobalTypeRegistry.h" +#include "Registries/SPIRVGlobalInstrRegistry.h" #include "SPIRVUtils.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallSet.h" @@ -31,7 +32,6 @@ namespace SPIRV { // The enum contains logical module sections for the instruction collection. enum ModuleSectionType { // MB_Capabilities, MB_Extensions, MB_ExtInstImports, MB_MemoryModel, - MB_EntryPoints, // All OpEntryPoint instructions (if any). // MB_ExecutionModes, MB_DebugSourceAndStrings, MB_DebugNames, // All OpName and OpMemberName intrs. MB_DebugModuleProcessed, // All OpModuleProcessed instructions. @@ -214,6 +214,7 @@ struct SPIRVModuleAnalysis : public ModulePass { const SPIRVSubtarget *ST; SPIRVGlobalTypeRegistry *GTR; + SPIRVGlobalInstrRegistry *GIR; const SPIRVInstrInfo *TII; MachineModuleInfo *MMI; }; diff --git a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp index a177fb2bda76..2a1d7f466c36 100644 --- a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp @@ -51,7 +51,9 @@ SPIRVSubtarget::SPIRVSubtarget(const Triple &TT, const std::string &CPU, initAvailableExtInstSets(); GTR = std::make_unique(PointerSize); - CallLoweringInfo = std::make_unique(TLInfo, GTR.get()); + GIR = std::make_unique(); + CallLoweringInfo = + std::make_unique(TLInfo, GTR.get(), GIR.get()); Legalizer = std::make_unique(*this); RegBankInfo = std::make_unique(); InstSelector.reset( diff --git a/llvm/lib/Target/SPIRV/SPIRVSubtarget.h b/llvm/lib/Target/SPIRV/SPIRVSubtarget.h index cf72da858f7f..4042f37fb495 100644 --- a/llvm/lib/Target/SPIRV/SPIRVSubtarget.h +++ b/llvm/lib/Target/SPIRV/SPIRVSubtarget.h @@ -17,6 +17,8 @@ #include "SPIRVFrameLowering.h" #include "SPIRVISelLowering.h" #include "SPIRVInstrInfo.h" +#include "Registries/SPIRVGlobalTypeRegistry.h" +#include "Registries/SPIRVGlobalInstrRegistry.h" #include "llvm/CodeGen/GlobalISel/CallLowering.h" #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" @@ -41,6 +43,7 @@ class SPIRVSubtarget : public SPIRVGenSubtargetInfo { SmallSet AvailableExtensions; SmallSet AvailableExtInstSets; std::unique_ptr GTR; + std::unique_ptr GIR; SPIRVInstrInfo InstrInfo; SPIRVFrameLowering FrameLowering; @@ -86,6 +89,10 @@ class SPIRVSubtarget : public SPIRVGenSubtargetInfo { return GTR.get(); } + SPIRVGlobalInstrRegistry *getSPIRVGlobalInstrRegistry() const { + return GIR.get(); + } + const CallLowering *getCallLowering() const override { return CallLoweringInfo.get(); } From 6c67dce056068768136adcd62de0c4518779a93b Mon Sep 17 00:00:00 2001 From: Michal Paszkowski Date: Tue, 11 Apr 2023 02:40:33 +0200 Subject: [PATCH 5/5] [SPIR-V] Don't emit OpName in MF --- .../Registries/SPIRVGlobalInstrRegistry.h | 31 ++++++++++++++++--- .../Registries/SPIRVGlobalTypeRegistry.cpp | 13 ++++---- .../Registries/SPIRVGlobalTypeRegistry.h | 5 ++- llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp | 15 ++++++++- llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 6 ++-- llvm/lib/Target/SPIRV/SPIRVBuiltins.h | 3 +- llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp | 5 +-- .../Target/SPIRV/SPIRVInstructionSelector.cpp | 13 +++----- llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 4 +-- llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h | 1 - llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 24 ++++++++++++-- llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp | 2 +- llvm/lib/Target/SPIRV/SPIRVUtils.cpp | 8 ----- llvm/lib/Target/SPIRV/SPIRVUtils.h | 4 --- 14 files changed, 89 insertions(+), 45 deletions(-) diff --git a/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalInstrRegistry.h b/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalInstrRegistry.h index dca188378733..1543a276bdb1 100644 --- a/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalInstrRegistry.h +++ b/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalInstrRegistry.h @@ -20,6 +20,7 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/IR/Function.h" +#include "llvm/CodeGen/MachineFunction.h" namespace llvm { namespace SPIRV { @@ -31,7 +32,17 @@ struct OpEntryPointInst { OpEntryPointInst(const SPIRV::ExecutionModel::ExecutionModel ExecModel, const Function *const EntryFunction) : ExecModel(ExecModel), EntryFunction(EntryFunction) {} - OpEntryPointInst &operator=(const OpEntryPointInst &) = delete; +}; + +/// Struct representing a global OpName instruction for later printing. +struct OpNameInst { + const Register NamedId; + const MachineFunction *const NamedIdFunction; + const std::string Name; + + OpNameInst(const Register NamedId, const MachineFunction *const NamedIdFunction, + const std::string Name) + : NamedId(NamedId), NamedIdFunction(NamedIdFunction), Name(Name) {} }; } // namespace SPIRV @@ -39,7 +50,8 @@ struct OpEntryPointInst { /// emitting SPIR-V global instructions. class SPIRVGlobalInstrRegistry { private: - SmallVector OpEntryPoints; + SmallVector OpEntryPointInsts; + SmallVector OpNameInsts; public: SPIRVGlobalInstrRegistry() {} @@ -47,12 +59,23 @@ class SPIRVGlobalInstrRegistry { /// Declare a new SPIR-V entry point. void addEntryPoint(const SPIRV::ExecutionModel::ExecutionModel ExecModel, const Function *const EntryFunction) { - OpEntryPoints.push_back(SPIRV::OpEntryPointInst(ExecModel, EntryFunction)); + OpEntryPointInsts.push_back( + SPIRV::OpEntryPointInst(ExecModel, EntryFunction)); } /// Get all already declared SPIR-V entry points. const SmallVector &getAllEntryPoints() const { - return OpEntryPoints; + return OpEntryPointInsts; + } + + void nameResultId(const Register NamedId, + const MachineFunction *const NamedIdFunction, + const std::string Name) { + OpNameInsts.push_back(SPIRV::OpNameInst(NamedId, NamedIdFunction, Name)); + } + + const SmallVector &getAllOpNameInst() const { + return OpNameInsts; } }; diff --git a/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.cpp b/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.cpp index e2de29162d8c..4282c87de0b6 100644 --- a/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.cpp +++ b/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.cpp @@ -22,8 +22,9 @@ #include "SPIRVUtils.h" using namespace llvm; -SPIRVGlobalTypeRegistry::SPIRVGlobalTypeRegistry(unsigned PointerSize) - : PointerSize(PointerSize) {} +SPIRVGlobalTypeRegistry::SPIRVGlobalTypeRegistry(unsigned PointerSize, + SPIRVGlobalInstrRegistry *GIR) + : PointerSize(PointerSize), GIR(GIR) {} SPIRVType *SPIRVGlobalTypeRegistry::assignIntTypeToVReg(unsigned BitWidth, Register VReg, @@ -503,7 +504,7 @@ Register SPIRVGlobalTypeRegistry::buildGlobalVariable( // If it's a global variable with name, output OpName for it. if (GVar && GVar->hasName()) - buildOpName(Reg, GVar->getName(), MIRBuilder); + GIR->nameResultId(Reg, &MIRBuilder.getMF(), GVar->getName().str()); // Output decorations for the GV. // TODO: maybe move to GenerateDecorations pass. @@ -549,7 +550,7 @@ SPIRVType *SPIRVGlobalTypeRegistry::getOpTypeOpaque(const StructType *Ty, Register ResVReg = createTypeVReg(MIRBuilder); auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeOpaque).addDef(ResVReg); addStringImm(Name, MIB); - buildOpName(ResVReg, Name, MIRBuilder); + GIR->nameResultId(ResVReg, &MIRBuilder.getMF(), Name.str()); return MIB; } @@ -568,7 +569,7 @@ SPIRVType *SPIRVGlobalTypeRegistry::getOpTypeStruct(const StructType *Ty, for (const auto &Ty : FieldTypes) MIB.addUse(Ty); if (Ty->hasName()) - buildOpName(ResVReg, Ty->getName(), MIRBuilder); + GIR->nameResultId(ResVReg, &MIRBuilder.getMF(), Ty->getName().str()); if (Ty->isPacked()) buildOpDecorate(ResVReg, MIRBuilder, SPIRV::Decoration::CPacked, {}); return MIB; @@ -584,7 +585,7 @@ SPIRVType *SPIRVGlobalTypeRegistry::getOrCreateSpecialType( Ty = PType->getNonOpaquePointerElementType(); } assert(isSpecialOpaqueType(Ty) && "Not a special opaque builtin type"); - return SPIRV::lowerBuiltinType(Ty, AccQual, MIRBuilder, this); + return SPIRV::lowerBuiltinType(Ty, AccQual, MIRBuilder, this, GIR); } SPIRVType *SPIRVGlobalTypeRegistry::getOpTypePointer( diff --git a/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.h b/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.h index fed5d92033ef..e7ec98d7910d 100644 --- a/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.h +++ b/llvm/lib/Target/SPIRV/Registries/SPIRVGlobalTypeRegistry.h @@ -19,6 +19,7 @@ #include "MCTargetDesc/SPIRVBaseInfo.h" #include "SPIRVDuplicatesTracker.h" #include "SPIRVInstrInfo.h" +#include "SPIRVGlobalInstrRegistry.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" namespace llvm { @@ -63,8 +64,10 @@ class SPIRVGlobalTypeRegistry { SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR); + SPIRVGlobalInstrRegistry *GIR; + public: - SPIRVGlobalTypeRegistry(unsigned PointerSize); + SPIRVGlobalTypeRegistry(unsigned PointerSize, SPIRVGlobalInstrRegistry *GIR); MachineFunction *CurMF; diff --git a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp index fe2322c8f221..afa2fe59193f 100644 --- a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp @@ -59,6 +59,7 @@ class SPIRVAsmPrinter : public AsmPrinter { void outputModuleSection(SPIRV::ModuleSectionType MSType); void outputGlobalRequirements(); void outputEntryPoints(); + void outputDebugNames(); void outputDebugSourceAndStrings(const Module &M); void outputOpExtInstImports(const Module &M); void outputOpMemoryModel(); @@ -246,6 +247,18 @@ void SPIRVAsmPrinter::outputModuleSection(SPIRV::ModuleSectionType MSType) { outputInstruction(MI); } +void SPIRVAsmPrinter::outputDebugNames() { + for (const SPIRV::OpNameInst &NI : GIR->getAllOpNameInst()) { + MCInst TmpInst; + TmpInst.setOpcode(SPIRV::OpName); + Register NewReg = MAI->getRegisterAlias(NI.NamedIdFunction, NI.NamedId); + TmpInst.addOperand( + MCOperand::createReg(NewReg.isValid() ? NewReg : NI.NamedId)); + addStringImm(NI.Name, TmpInst); + outputMCInst(TmpInst); + } +} + void SPIRVAsmPrinter::outputDebugSourceAndStrings(const Module &M) { // Output OpSourceExtensions. for (auto &Str : MAI->SrcExt) { @@ -523,7 +536,7 @@ void SPIRVAsmPrinter::outputModuleSections() { // OpSourceContinued, without forward references. outputDebugSourceAndStrings(*M); // 7b. Debug: all OpName and all OpMemberName. - outputModuleSection(SPIRV::MB_DebugNames); + outputDebugNames(); // 7c. Debug: all OpModuleProcessed instructions. outputModuleSection(SPIRV::MB_DebugModuleProcessed); // 8. All annotation instructions (all decorations). diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp index 50b39bb9df58..0334d3f3b668 100644 --- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp @@ -2070,7 +2070,8 @@ namespace SPIRV { SPIRVType *lowerBuiltinType(const Type *OpaqueType, SPIRV::AccessQualifier::AccessQualifier AccessQual, MachineIRBuilder &MIRBuilder, - SPIRVGlobalTypeRegistry *GTR) { + SPIRVGlobalTypeRegistry *GTR, + SPIRVGlobalInstrRegistry *GIR) { // In LLVM IR, SPIR-V and OpenCL builtin types are represented as either // target(...) target extension types or pointers-to-opaque-structs. The // approach relying on structs is deprecated and works only in the non-opaque @@ -2123,7 +2124,8 @@ SPIRVType *lowerBuiltinType(const Type *OpaqueType, // Emit OpName instruction if a new OpType<...> instruction was added // (equivalent type was not found in GlobalRegistry). if (NumStartingVRegs < MIRBuilder.getMRI()->getNumVirtRegs()) - buildOpName(GTR->getSPIRVTypeID(TargetType), Name, MIRBuilder); + GIR->nameResultId(GTR->getSPIRVTypeID(TargetType), &MIRBuilder.getMF(), + Name.str()); return TargetType; } diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.h b/llvm/lib/Target/SPIRV/SPIRVBuiltins.h index ca2d49d5455e..191c81e104b9 100644 --- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.h +++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.h @@ -48,7 +48,8 @@ std::optional lowerBuiltin(const StringRef DemangledCall, SPIRVType *lowerBuiltinType(const Type *Type, AccessQualifier::AccessQualifier AccessQual, MachineIRBuilder &MIRBuilder, - SPIRVGlobalTypeRegistry *GTR); + SPIRVGlobalTypeRegistry *GTR, + SPIRVGlobalInstrRegistry *GIR); } // namespace SPIRV } // namespace llvm #endif // LLVM_LIB_TARGET_SPIRV_SPIRVBUILTINS_H diff --git a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp index 8348893e013a..735627a16f39 100644 --- a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp @@ -240,7 +240,8 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, ArgTypeVRegs.push_back(SpirvTy); if (Arg.hasName()) - buildOpName(VRegs[i][0], Arg.getName(), MIRBuilder); + GIR->nameResultId(VRegs[i][0], &MIRBuilder.getMF(), + Arg.getName().str()); if (Arg.getType()->isPointerTy()) { auto DerefBytes = static_cast(Arg.getDereferenceableBytes()); if (DerefBytes != 0) @@ -337,7 +338,7 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, } // Name the function. if (F.hasName()) - buildOpName(FuncVReg, F.getName(), MIRBuilder); + GIR->nameResultId(FuncVReg, &MIRBuilder.getMF(), F.getName().str()); // Handle entry points and function linkage. if (F.getCallingConv() == CallingConv::SPIR_KERNEL) { diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index 636bb2e33e66..fabaf540e618 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -14,6 +14,7 @@ #include "SPIRV.h" #include "Registries/SPIRVGlobalTypeRegistry.h" +#include "Registries/SPIRVGlobalInstrRegistry.h" #include "SPIRVInstrInfo.h" #include "SPIRVRegisterBankInfo.h" #include "SPIRVRegisterInfo.h" @@ -48,6 +49,8 @@ class SPIRVInstructionSelector : public InstructionSelector { const SPIRVRegisterInfo &TRI; const RegisterBankInfo &RBI; SPIRVGlobalTypeRegistry >R; + SPIRVGlobalInstrRegistry &GIR; + MachineRegisterInfo *MRI; public: @@ -192,6 +195,7 @@ SPIRVInstructionSelector::SPIRVInstructionSelector(const SPIRVTargetMachine &TM, : InstructionSelector(), STI(ST), TII(*ST.getInstrInfo()), TRI(*ST.getRegisterInfo()), RBI(RBI), GTR(*ST.getSPIRVGlobalTypeRegistry()), + GIR(*ST.getSPIRVGlobalInstrRegistry()), #define GET_GLOBALISEL_PREDICATES_INIT #include "SPIRVGenGlobalISel.inc" #undef GET_GLOBALISEL_PREDICATES_INIT @@ -1363,15 +1367,6 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, } return MIB.constrainAllUses(TII, TRI, RBI); } - case Intrinsic::spv_assign_name: { - auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpName)); - MIB.addUse(I.getOperand(I.getNumExplicitDefs() + 1).getReg()); - for (unsigned i = I.getNumExplicitDefs() + 2; - i < I.getNumExplicitOperands(); ++i) { - MIB.addImm(I.getOperand(i).getImm()); - } - return MIB.constrainAllUses(TII, TRI, RBI); - } case Intrinsic::spv_switch: { auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSwitch)); for (unsigned i = 1; i < I.getNumExplicitOperands(); ++i) { diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp index f7535760a62c..c9a64559f1fa 100644 --- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp @@ -336,9 +336,7 @@ void SPIRVModuleAnalysis::processOtherInstrs(const Module &M) { if (MAI.getSkipEmission(&MI)) continue; const unsigned OpCode = MI.getOpcode(); - if (OpCode == SPIRV::OpName || OpCode == SPIRV::OpMemberName) { - collectOtherInstr(MI, MAI, SPIRV::MB_DebugNames); - } else if (TII->isDecorationInstr(MI)) { + if (TII->isDecorationInstr(MI)) { collectOtherInstr(MI, MAI, SPIRV::MB_Annotations); collectFuncNames(MI, &*F); } else if (TII->isConstantInstr(MI)) { diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h index 6027a1dec429..f1f6501143ad 100644 --- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h +++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h @@ -33,7 +33,6 @@ namespace SPIRV { enum ModuleSectionType { // MB_Capabilities, MB_Extensions, MB_ExtInstImports, MB_MemoryModel, // MB_ExecutionModes, MB_DebugSourceAndStrings, - MB_DebugNames, // All OpName and OpMemberName intrs. MB_DebugModuleProcessed, // All OpModuleProcessed instructions. MB_Annotations, // OpDecorate, OpMemberDecorate etc. MB_TypeConstVars, // OpTypeXXX, OpConstantXXX, and global OpVariables. diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp index 9327c8ecbdd8..89255488e33e 100644 --- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp @@ -224,7 +224,7 @@ Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy, } } // namespace llvm -static void generateAssignInstrs(MachineFunction &MF, +static void generateAssignTypeInstrs(MachineFunction &MF, SPIRVGlobalTypeRegistry *GTR, MachineIRBuilder MIB) { MachineRegisterInfo &MRI = MF.getRegInfo(); @@ -302,6 +302,24 @@ static void generateAssignInstrs(MachineFunction &MF, MI->eraseFromParent(); } +static void processAssignNameInstrs(MachineFunction &MF, + SPIRVGlobalInstrRegistry *GIR) { + SmallVector ToErase; + for (MachineBasicBlock &MBB : MF) { + for (MachineInstr &MI : MBB) { + if (!isSpvIntrinsic(MI, Intrinsic::spv_assign_name)) + continue; + + std::string Name = getStringImm(MI, 2); + GIR->nameResultId(MI.getOperand(MI.getNumExplicitDefs() + 1).getReg(), + &MF, Name); + ToErase.push_back(&MI); + } + } + for (MachineInstr *MI : ToErase) + MI->eraseFromParent(); +} + static std::pair createNewIdReg(Register ValReg, unsigned Opcode, MachineRegisterInfo &MRI, const SPIRVGlobalTypeRegistry >R) { @@ -576,12 +594,14 @@ bool SPIRVPreLegalizer::runOnMachineFunction(MachineFunction &MF) { // Initialize the type registry. const SPIRVSubtarget &ST = MF.getSubtarget(); SPIRVGlobalTypeRegistry *GTR = ST.getSPIRVGlobalTypeRegistry(); + SPIRVGlobalInstrRegistry *GIR = ST.getSPIRVGlobalInstrRegistry(); GTR->setCurrentFunc(MF); MachineIRBuilder MIB(MF); addConstantsToTrack(MF, GTR); foldConstantsIntoIntrinsics(MF); insertBitcasts(MF, GTR, MIB); - generateAssignInstrs(MF, GTR, MIB); + generateAssignTypeInstrs(MF, GTR, MIB); + processAssignNameInstrs(MF, GIR); processSwitches(MF, GTR, MIB); processInstrsWithTypeFolding(MF, GTR, MIB); diff --git a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp index 2a1d7f466c36..bf17f27b360d 100644 --- a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp @@ -50,8 +50,8 @@ SPIRVSubtarget::SPIRVSubtarget(const Triple &TT, const std::string &CPU, initAvailableExtensions(); initAvailableExtInstSets(); - GTR = std::make_unique(PointerSize); GIR = std::make_unique(); + GTR = std::make_unique(PointerSize, GIR.get()); CallLoweringInfo = std::make_unique(TLInfo, GTR.get(), GIR.get()); Legalizer = std::make_unique(*this); diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp index 514dc6497c47..b9e89ce4b57f 100644 --- a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp @@ -92,14 +92,6 @@ void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB) { report_fatal_error("Unsupported constant bitwidth"); } -void buildOpName(Register Target, const StringRef &Name, - MachineIRBuilder &MIRBuilder) { - if (!Name.empty()) { - auto MIB = MIRBuilder.buildInstr(SPIRV::OpName).addUse(Target); - addStringImm(Name, MIB); - } -} - static void finishBuildOpDecorate(MachineInstrBuilder &MIB, const std::vector &DecArgs, StringRef StrImm) { diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.h b/llvm/lib/Target/SPIRV/SPIRVUtils.h index 7c193611a857..245d748e68ff 100644 --- a/llvm/lib/Target/SPIRV/SPIRVUtils.h +++ b/llvm/lib/Target/SPIRV/SPIRVUtils.h @@ -43,10 +43,6 @@ std::string getStringImm(const MachineInstr &MI, unsigned StartIndex); // Add the given numerical immediate to MIB. void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB); -// Add an OpName instruction for the given target register. -void buildOpName(Register Target, const StringRef &Name, - MachineIRBuilder &MIRBuilder); - // Add an OpDecorate instruction for the given Reg. void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec,