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[snippy] implement random scheduling deoptimization
This patch implements deoptimization of the generated snippet by reordering instructions. It is guaranteed that the final state of the register file and memory remains the same. The algorithm involves the following steps: 1) A dependency graph of instructions is built based on RAW, WAR, and WAW dependencies. 2) An arbitrary reverse post order (RPO) traversal of this graph is selected. 3) The code is reordered according to the chosen approach. In practice, multiple different graphs must be constructed to preserve control flow as well as the observed behavior regarding instructions with non-trivial semantics (e.g., fence).
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‎llvm/test/tools/llvm-snippy/Inputs/random-scheduling/basic.yaml‎

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scheduling:
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enabled: true
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max-region-size: 1000

‎llvm/test/tools/llvm-snippy/patterns/histogram-patterns/random-scheduling-with-patterns.yaml‎

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# RUN: llvm-snippy %s -model-plugin=None -verify-mi |& FileCheck %s
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options:
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mtriple: riscv64
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dump-mf: on
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mattr: "+c"
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num-instrs: 10000
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verify-gen-histogram: on
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histogram-must-succeed: on
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scheduling:
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enabled: on
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max-region-size: 250
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include:
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- Inputs/sections.yaml
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histogram-patterns:
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- LdSd: "AND * (LD ^ 10) * SUB * (SD ^ 5)"
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- C_LdSd: "(C_LW ^ 5) * C_LD | (C_SW ^ 3) * C_SD"
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histogram:
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- [pattern: LdSd, 11]
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- [pattern: C_LdSd, 11]
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- [LB, 11]
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- [LBU, 11]
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- [LH, 11]
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- [LHU, 11]
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- [LW, 11]
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- [LWU, 11]
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- [SB, 16]
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- [SH, 16]
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- [PseudoNOP, 5]
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# CHECK-DAG: LB
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# CHECK-DAG: LBU
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# CHECK-DAG: LH
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# CHECK-DAG: LHU
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# CHECK-DAG: LW
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# CHECK-DAG: SB
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# CHECK-DAG: SH
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# CHECK-DAG: PseudoNOP
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# COM: Chekc LdSd pattern
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# CHECK: AND
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: SUB
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# CHECK-NEXT: SD
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# CHECK-NEXT: SD
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# CHECK-NEXT: SD
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# CHECK-NEXT: SD
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# CHECK-NEXT: SD
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# COM: Chekc LdSd pattern
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# CHECK: AND
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: SUB
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# CHECK-NEXT: SD
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# CHECK-NEXT: SD
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# CHECK-NEXT: SD
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# CHECK-NEXT: SD
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# CHECK-NEXT: SD
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# COM: Chekc C_LdSd pattern
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# CHECK: C_LW
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# CHECK-NEXT: C_LW
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# CHECK-NEXT: C_LW
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# CHECK-NEXT: C_LW
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# CHECK-NEXT: C_LW
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# CHECK-NEXT: C_LD
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# COM: Chekc C_LdSd pattern
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# CHECK: C_SW
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# CHECK-NEXT: C_SW
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# CHECK-NEXT: C_SW
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# CHECK-NEXT: C_SD
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# COM: Chekc C_LdSd pattern
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# CHECK: C_LW
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# CHECK-NEXT: C_LW
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# CHECK-NEXT: C_LW
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# CHECK-NEXT: C_LW
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# CHECK-NEXT: C_LW
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# CHECK-NEXT: C_LD
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# COM: Chekc C_LdSd pattern
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# CHECK: C_SW
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# CHECK-NEXT: C_SW
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# CHECK-NEXT: C_SW
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# CHECK-NEXT: C_SD

‎llvm/test/tools/llvm-snippy/random-scheduling-barriers.yaml‎

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# REQUIRES: asserts
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# RUN: llvm-snippy %s \
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# RUN: -mtriple=riscv64 -model-plugin=None \
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# RUN: -num-instrs=10000 -init-regs-in-elf -debug-only=snippy-riscv \
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# RUN: -initial-regs=%S/initialization/Inputs/initial_state_rv64i.yaml \
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# RUN: -random-scheduling \
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# RUN: |& FileCheck %s
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options:
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mattr: +zifencei
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sections:
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- name: 0
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VMA: 0x10000
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SIZE: 0x40000
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LMA: 0x10000
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ACCESS: r
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- name: 1
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VMA: 0x100000
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SIZE: 0x100000
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LMA: 0x100000
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ACCESS: rx
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- name: 2
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VMA: 0x210000
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SIZE: 0x100000
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LMA: 0x210000
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ACCESS: rw
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histogram:
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# branches
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- [BEQ, 3.7]
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- [BGE, 3.7]
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- [BGEU, 3.7]
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- [BLT, 3.7]
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- [BLTU, 3.7]
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- [BNE, 3.7]
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- [ECALL, 10.0]
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- [WFI, 10.0]
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- [FENCE, 10.0]
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- [FENCE_I, 10.0]
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- [SFENCE_VMA, 10.0]
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- [UNIMP, 10.0]
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- [AUIPC, 10.0]
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- [SW, 1.0]
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- [ADD, 1.0]
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- [XOR, 1.0]
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- [AND, 1.0]
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- [SUB, 1.0]
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branches:
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number-of-loop-iterations:
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min: 1
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max: 2
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max-depth:
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if: 3
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loop: 3
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# CHECK-DAG: Unsupported scheduling instruction : {{((\$x([0-9]+)))}} = AUIPC
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# CHECK-DAG: Unsupported scheduling instruction : ECALL
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# CHECK-DAG: Unsupported scheduling instruction : WFI
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# CHECK-DAG: Unsupported scheduling instruction : FENCE
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# CHECK-DAG: Unsupported scheduling instruction : FENCE_I
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# CHECK-DAG: Unsupported scheduling instruction : SFENCE_VMA
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# CHECK-DAG: Unsupported scheduling instruction : UNIMP

‎llvm/test/tools/llvm-snippy/random-scheduling-burst.yaml‎

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# RUN: llvm-snippy %s | FileCheck %s
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options:
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mtriple: riscv64
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mattr: "+m,+v"
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num-instrs: 10000
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dump-mf: on
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verify-gen-histogram: on
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histogram-must-succeed: on
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include:
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- Inputs/sections.yaml
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scheduling:
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enabled: on
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burst:
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mode: custom
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min-size: 5
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max-size: 5
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groupings:
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- [LD]
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- [SD]
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- [LW]
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- [SW]
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- [VLE8_V]
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- [VADD_VX]
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- [VLSEG2E32_V]
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- [VL2RE8_V]
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- [VS2R_V]
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histogram:
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- [LD, 1.0]
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- [SD, 1.0]
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- [LW, 1.0]
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- [SW, 1.0]
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- [VSETVL, 0.5]
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- [VLE8_V, 1.0]
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- [VADD_VX, 1.0]
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- [VLSEG2E32_V, 1.0]
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- [VL2RE8_V, 1.0]
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- [VS2R_V, 1.0]
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- [MUL, 1.0]
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- [DIV, 1.0]
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- [SUB, 1.0]
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# CHECK-DAG: MUL
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# CHECK-DAG: DIV
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# CHECK-DAG: SUB
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# CHECK: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK-NEXT: LD
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# CHECK: SD
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# CHECK-NEXT: SD
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# CHECK-NEXT: SD
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# CHECK-NEXT: SD
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# CHECK-NEXT: SD
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# CHECK: LW
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# CHECK-NEXT: LW
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# CHECK-NEXT: LW
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# CHECK-NEXT: LW
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# CHECK-NEXT: LW
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# CHECK: SW
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# CHECK-NEXT: SW
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# CHECK-NEXT: SW
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# CHECK-NEXT: SW
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# CHECK-NEXT: SW
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# CHECK: VLE8_V
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# CHECK-NEXT: VLE8_V
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# CHECK-NEXT: VLE8_V
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# CHECK-NEXT: VLE8_V
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# CHECK-NEXT: VLE8_V
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# CHECK: VADD_V
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# CHECK-NEXT: VADD_V
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# CHECK-NEXT: VADD_V
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# CHECK-NEXT: VADD_V
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# CHECK-NEXT: VADD_V
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# CHECK: VLSEG2E32_V
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# CHECK-NEXT: VLSEG2E32_V
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# CHECK-NEXT: VLSEG2E32_V
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# CHECK-NEXT: VLSEG2E32_V
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# CHECK-NEXT: VLSEG2E32_V
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# CHECK: VL2RE8_V
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# CHECK-NEXT: VL2RE8_V
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# CHECK-NEXT: VL2RE8_V
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# CHECK-NEXT: VL2RE8_V
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# CHECK-NEXT: VL2RE8_V
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# CHECK: VS2R_V
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# CHECK-NEXT: VS2R_V
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# CHECK-NEXT: VS2R_V
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# CHECK-NEXT: VS2R_V
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# CHECK-NEXT: VS2R_V

‎llvm/test/tools/llvm-snippy/random-scheduling-calls.yaml‎

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# REQUIRES: asserts
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# RUN: llvm-snippy %S/Inputs/jal-layout.yaml %s \
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# RUN: -mtriple=riscv64 -enable-static-stack=false \
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# RUN: -num-instrs=10000 -mattr=+c \
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# RUN: -initial-regs=%S/initialization/Inputs/initial_state_rv64i.yaml \
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# RUN: -o %t_1
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# RUN: llvm-snippy %S/Inputs/jal-layout.yaml %s \
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# RUN: -mtriple=riscv64 -enable-static-stack=false \
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# RUN: -num-instrs=10000 -mattr=+c -debug-only=snippy-riscv \
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# RUN: -initial-regs=%S/initialization/Inputs/initial_state_rv64i.yaml \
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# RUN: -o %t_2 -random-scheduling \
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# RUN: |& FileCheck %s
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# RUN: not diff -q %t_1.elf %t_2.elf
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call-graph:
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entry-point: SnippyFunction
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function-list:
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- name: SnippyFunction
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callees:
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- fun1
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- fun2
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- name: fun1
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callees:
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- fun2
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- name: fun2
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callees:
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- fun3
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- name: fun3
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# CHECK: Currently unsupported scheduling instruction : ${{[a-z0-9]+}} = PseudoJALCall

‎llvm/test/tools/llvm-snippy/random-scheduling-floats.yaml‎

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# RUN: llvm-snippy %s \
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# RUN: -mtriple=riscv64 \
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# RUN: -num-instrs=10000 -init-regs-in-elf -o %t_1 \
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# RUN: -mattr=+c,+f \
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# RUN: -initial-regs=%S/initialization/Inputs/initial_state_rv64i.yaml
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# RUN: llvm-snippy %s \
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# RUN: -mtriple=riscv64 \
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# RUN: -num-instrs=10000 -init-regs-in-elf -o %t_2 \
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# RUN: -mattr=+c,+f -random-scheduling \
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# RUN: -initial-regs=%S/initialization/Inputs/initial_state_rv64i.yaml
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# RUN: not diff -q %t_1.elf %t_2.elf
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sections:
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- name: 1
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VMA: 0x100000
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SIZE: 0x1000000
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LMA: 0x100000
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ACCESS: rx
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- name: 2
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VMA: 0x1100000
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SIZE: 0x100000
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LMA: 0x1100000
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ACCESS: rw
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histogram:
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# branches ~ every 30 instructions
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- [BEQ, 3.7]
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- [BGE, 3.7]
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- [BGEU, 3.7]
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- [BLT, 3.7]
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- [BLTU, 3.7]
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- [BNE, 3.7]
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- [C_BEQZ, 3.7]
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- [C_BNEZ, 3.7]
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- [C_J, 3.7]
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# Floats
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- [FMADD_S, 1.0]
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- [FMSUB_S, 1.0]
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- [FNMSUB_S, 1.0]
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- [FNMADD_S, 1.0]
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- [FADD_S, 1.0]
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- [FSUB_S, 1.0]
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- [FMUL_S, 1.0]
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- [FDIV_S, 1.0]
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- [FSQRT_S, 1.0]
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- [FSGNJ_S, 1.0]
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- [FSGNJN_S, 1.0]
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- [FSGNJX_S, 1.0]
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- [FMIN_S, 1.0]
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- [FMAX_S, 1.0]
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- [FCVT_W_S, 1.0]
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- [FCVT_WU_S, 1.0]
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- [FMV_X_W, 1.0]
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- [FEQ_S, 1.0]
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- [FLT_S, 1.0]
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- [FLE_S, 1.0]
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- [FCLASS_S, 1.0]
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- [FCVT_S_W, 1.0]
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- [FCVT_S_WU, 1.0]
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- [FMV_W_X, 1.0]
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- [FCVT_L_S, 1.0]
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- [FCVT_LU_S, 1.0]
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- [FCVT_S_L, 1.0]
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- [FCVT_S_LU, 1.0]
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- [FLW, 1.0]
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- [FSW, 1.0]
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- [SW, 5.0]
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- [ADD, 5.0]
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- [XOR, 5.0]
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- [AND, 5.0]
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- [SUB, 5.0]
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branches:
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number-of-loop-iterations:
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min: 1
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max: 2
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max-depth:
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if: 3
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loop: 3
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