ci.yml

name: rtl-ci

on:
  push:
  pull_request:
  workflow_dispatch:

permissions:
  contents: read

jobs:
  verify:
    runs-on: ubuntu-latest
    timeout-minutes: 10

    steps:
      - name: Check out repository
        uses: actions/checkout@v4

      - name: Set up Python
        uses: actions/setup-python@v5
        with:
          python-version: "3.12"

      - name: Install open-source RTL tools
        run: |
          sudo apt-get update
          sudo apt-get install -y iverilog yosys

      - name: Test Python golden model
        run: python -m unittest discover -s tests -v

      - name: Regress single-lane parameter case
        run: python tools/run_regression.py --sim iverilog --vec-len 1 --random-cases 40

      - name: Regress default vector length
        run: python tools/run_regression.py --sim iverilog --vec-len 8 --random-cases 200

      - name: Regress non-power-of-two vector length
        run: python tools/run_regression.py --sim iverilog --vec-len 17 --random-cases 100

      - name: Run Yosys structural synthesis check
        run: >-
          yosys -p 'read_verilog -sv -DSYNTHESIS rtl/int8_dot_product.sv;
          chparam -set VEC_LEN 8 int8_dot_product;
          hierarchy -check -top int8_dot_product;
          proc; opt; check -assert; stat'