Added support for STREXB instruction

Author: kingofpayne

README.md

@@ -51,7 +51,6 @@ Here is a list of instructions that are not implemented yet for ArmV7-M archiect
 - PSSBB: Physical Speculative Store Bypass Barrier
 - SSBB: Speculative Store Bypass Barrier
 - STRBT: Store Register Byte Unprivileged
-- STREXB: Store Register Exclusive Byte
 - STREXH: Store Register Exclusive Halfword
 - STRHT: Store Register Halfword Unprivileged
 - STRT: Store Register Unprivileged
@@ -151,7 +150,6 @@ Here is the list of instructions that are not implemented yet for ArmV8-M archit
 - STLEXH: Store-Release Exclusive Halfword
 - STLH: Store-Release Halfword
 - STRBT: Store Register Byte Unprivileged
-- STREXB: Store Register Exclusive Byte
 - STREXH: Store Register Exclusive Halfword
 - STRHT: Store Register Halfword Unprivileged
 - STRT: Store Register Unprivileged

src/decoder.rs

@@ -407,6 +407,7 @@ impl BasicInstructionDecoder {
         dec.insert::<instructions::strb::StrbReg>(version);
         dec.insert::<instructions::strd::StrdImm>(version);
         dec.insert::<instructions::strex::Strex>(version);
+        dec.insert::<instructions::strexb::Strexb>(version);
         dec.insert::<instructions::strh::StrhImm>(version);
         dec.insert::<instructions::strh::StrhReg>(version);
         dec.insert::<instructions::sub::SubImm>(version);

src/instructions/mod.rs

@@ -104,6 +104,7 @@ pub mod str;
 pub mod strb;
 pub mod strd;
 pub mod strex;
+pub mod strexb;
 pub mod strh;
 pub mod sub;
 pub mod svc;

src/instructions/strexb.rs

@@ -0,0 +1,64 @@
+//! Implements STREXB (Store Register Exclusive Byte) instruction.
+
+use super::{Encoding::T1, Pattern};
+use crate::{
+    core::{
+        ArmVersion::{V7EM, V7M, V8M},
+        Effect, ItState, Processor, RunError,
+    },
+    decoder::DecodeError,
+    instructions::{unpredictable, DecodeHelper, Encoding, Instruction},
+    registers::RegisterIndex,
+};
+
+/// STREXB instruction.
+///
+/// Store Register Exclusive Byte.
+pub struct Strexb {
+    /// Destination register for the returned status value.
+    rd: RegisterIndex,
+    /// Source register.
+    rt: RegisterIndex,
+    /// Base register.
+    rn: RegisterIndex,
+}
+
+impl Instruction for Strexb {
+    fn patterns() -> &'static [Pattern] {
+        &[Pattern {
+            encoding: T1,
+            versions: &[V7M, V7EM, V8M],
+            expression: "111010001100xxxxxxxx(1)(1)(1)(1)0100xxxx",
+        }]
+    }
+
+    fn try_decode(encoding: Encoding, ins: u32, _state: ItState) -> Result<Self, DecodeError> {
+        debug_assert_eq!(encoding, T1);
+        let rd = ins.reg4(0);
+        let rt = ins.reg4(12);
+        let rn = ins.reg4(16);
+        unpredictable(rd.is_sp_or_pc() || rt.is_sp_or_pc() || rn.is_pc())?;
+        unpredictable(rd == rn || rd == rt)?;
+        Ok(Self { rd, rt, rn })
+    }
+
+    fn execute(&self, proc: &mut Processor) -> Result<Effect, RunError> {
+        let address = proc[self.rn];
+        if proc.exclusive_monitors_pass(address, 1)? {
+            let value = proc[self.rt] as u8;
+            proc.write_u8(address, value)?;
+            proc.set(self.rd, 0);
+        } else {
+            proc.set(self.rd, 1);
+        }
+        Ok(Effect::None)
+    }
+
+    fn name(&self) -> String {
+        "strexb".into()
+    }
+
+    fn args(&self, _pc: u32) -> String {
+        format!("{}, {}, [{}]", self.rd, self.rt, self.rn)
+    }
+}

src/test_decoder.txt

@@ -888,6 +888,11 @@ e4e98c26 strd     r2, r6, [r4, #560]!
 44e8ffca strex    r10, r12, [r4, #1020]
 44e8ff29 strex    r9, r2, [r4, #1020]
 4de8ff7c strex    r12, r7, [sp, #1020]
+c9e8403f strexb   r0, r3, [r9]
+c6e847af strexb   r7, r10, [r6]
+c7e84c9f strexb   r12, r9, [r7]
+cee8430f strexb   r3, r0, [lr]
+c1e8462f strexb   r6, r2, [r1]
 0880     strh     r0, [r1]
 ba80     strh     r2, [r7, #4]
 dd83     strh     r5, [r3, #30]

tests/encode.s

@@ -1431,6 +1431,14 @@ strex   r10, r12, [r4, #1020]
 strex   r9, r2, [r4, #1020]
 strex   r12, r7, [r13, #1020]
 
+// STREXB
+// T1
+strexb  r0, r3, [r9]
+strexb  r7, r10, [r6]
+strexb  r12, r9, [r7]
+strexb  r3, r0, [r14]
+strexb  r6, r2, [r1]
+
 // STRH (immediate)
 // T1
 strh.n  r0, [r1]