Added support for MCRR instruction

Author: kingofpayne

README.md

@@ -48,7 +48,6 @@ Here is a list of instructions that are not implemented yet for ArmV7-M archiect
 - LDREXH: Load Register Exclusive Halfword
 - LDRSBT: Load Register Signed Byte Unprivileged
 - LDRSHT: Load Register Signed Halfword Unprivileged
-- MCRR, MCRR2: Move to Compressor from two ARM Registers
 - MRC, MRC2: Move to Register from Coprocessor
 - MRRC, MRRC2: Move to two Registers from Compressor
 - PLD: Preload Data
@@ -149,7 +148,6 @@ Here is the list of instructions that are not implemented yet for ArmV8-M archit
 - LDRSHT: Load Register Signed Halfword Unprivileged
 - LSLS: Logical Shift Left, Setting flags
 - LSRS: Logical Shift Right, Setting flags
-- MCRR, MCRR2: Move to Compressor from two ARM Registers
 - MRC, MRC2: Move to ARM Register from Coprocessor
 - MRRC, MRRC2: Move to two ARM Registers from Coprocessor
 - PLD: Preload Data

src/decoder.rs

@@ -345,6 +345,7 @@ impl BasicInstructionDecoder {
         dec.insert::<instructions::lsr::LsrImm>(version);
         dec.insert::<instructions::lsr::LsrReg>(version);
         dec.insert::<instructions::mcr::Mcr>(version);
+        dec.insert::<instructions::mcrr::Mcrr>(version);
         dec.insert::<instructions::mla::Mla>(version);
         dec.insert::<instructions::mls::Mls>(version);
         dec.insert::<instructions::mov::MovImm>(version);

src/instructions/mcrr.rs

@@ -0,0 +1,99 @@
+//! Implements MCRR and MCRR2 (Move to Coprocessor from two Arm Registers) instructions.
+
+use super::{
+    Encoding::{self, T1, T2},
+    Instruction, Pattern,
+};
+use crate::{
+    arm::{
+        ArmProcessor,
+        ArmVersion::{V7EM, V7M, V8M},
+        Effect, RunError,
+    },
+    decoder::DecodeError,
+    instructions::{unpredictable, DecodeHelper},
+    it_state::ItState,
+    registers::RegisterIndex,
+};
+
+/// MCRR or MCRR2 instruction.
+///
+/// Move to Coprocessor from two Arm Registers.
+pub struct Mcrr {
+    /// Coprocessor index, from 0 to 15.
+    coproc: u8,
+    /// Coprocessor-specific opcode, from 0 to 15.
+    opc1: u8,
+    /// First Arm source register.
+    rt: RegisterIndex,
+    /// Second Arm source register.
+    rt2: RegisterIndex,
+    /// Additional coprocessor destination register, from 0 to 15.
+    crm: u8,
+    /// Encoding.
+    encoding: Encoding,
+    /// Raw encoding.
+    /// Required since transmitted directly to the coprocessor.
+    ins: u32,
+}
+
+impl Instruction for Mcrr {
+    fn patterns() -> &'static [Pattern] {
+        &[
+            Pattern {
+                encoding: T1,
+                versions: &[V7M, V7EM, V8M],
+                expression: "111011000100xxxxxxxxxxxxxxxxxxxx",
+            },
+            Pattern {
+                encoding: T2,
+                versions: &[V7M, V7EM, V8M],
+                expression: "111111000100xxxxxxxxxxxxxxxxxxxx",
+            },
+        ]
+    }
+
+    fn try_decode(encoding: Encoding, ins: u32, _state: ItState) -> Result<Self, DecodeError> {
+        debug_assert!((encoding == T1) || (encoding == T2));
+        let rt = ins.reg4(12);
+        let rt2 = ins.reg4(16);
+        unpredictable(rt.is_sp_or_pc() || rt2.is_sp_or_pc())?;
+        Ok(Self {
+            coproc: ins.imm4(8) as u8,
+            opc1: ins.imm4(4) as u8,
+            rt: ins.reg4(12),
+            rt2: ins.reg4(16),
+            crm: ins.imm4(0) as u8,
+            encoding,
+            ins,
+        })
+    }
+
+    fn execute(&self, proc: &mut ArmProcessor) -> Result<Effect, RunError> {
+        let Some(coprocessor) = proc.coproc_accepted(self.coproc, self.ins) else {
+            proc.generate_coprocessor_exception();
+            return Ok(Effect::None);
+        };
+
+        coprocessor
+            .borrow_mut()
+            .send_two_words(proc[self.rt2], proc[self.rt], self.ins);
+        Ok(Effect::None)
+    }
+
+    fn name(&self) -> String {
+        match self.encoding {
+            Encoding::T1 => "mcrr",
+            Encoding::T2 => "mcrr2",
+            _ => panic!(),
+        }
+        .into()
+    }
+
+    fn args(&self, _pc: u32) -> String {
+        format!(
+            "p{}, #{}, {}, {}, c{}",
+            self.coproc, self.opc1, self.rt, self.rt2, self.crm
+        )
+    }
+}

src/instructions/mod.rs

@@ -53,6 +53,7 @@ pub mod ldrt;
 pub mod lsl;
 pub mod lsr;
 pub mod mcr;
+pub mod mcrr;
 pub mod mla;
 pub mod mls;
 pub mod mov;

src/test_decoder.txt

@@ -491,6 +491,16 @@ efee777f mcr      p15, #7, r7, c15, c7, #3
 87fef1e3 mcr2     p3, #4, lr, c7, c1, #7
 effe777f mcr2     p15, #7, r7, c15, c7, #3
 22fe1f62 mcr2     p2, #1, r6, c2, c15, #0
+4eec0010 mcrr     p0, #0, r1, lr, c0
+41ec3975 mcrr     p5, #3, r7, r1, c9
+40ec73e7 mcrr     p7, #7, lr, r0, c3
+47ecf1ae mcrr     p14, #15, r10, r7, c1
+49ec6f72 mcrr     p2, #6, r7, r9, c15
+4efc0010 mcrr2    p0, #0, r1, lr, c0
+41fc3975 mcrr2    p5, #3, r7, r1, c9
+40fc73e7 mcrr2    p7, #7, lr, r0, c3
+47fcf1ae mcrr2    p14, #15, r10, r7, c1
+49fc6f72 mcrr2    p2, #6, r7, r9, c15
 01fb0230 mla      r0, r1, r2, r3
 05fb0074 mla      r4, r5, r0, r7
 07fb0809 mla      r9, r7, r8, r0
@@ -584,6 +594,7 @@ aff30080 nop.w
 66eac372 orn      r2, r6, r3, lsl #31
 70ea9e27 orns     r7, r0, lr, lsr #10
 7eea6810 orns     r0, lr, r8, asr #5
+0000     movs     r0, r0
 41f00000 orr      r0, r1, #0
 42f0aa21 orr      r1, r2, #2852170240
 43f4ff72 orr      r2, r3, #510
@@ -1017,3 +1028,4 @@ aff30180 yield.w
 aff30280 wfe.w
 30bf     wfi
 aff30380 wfi.w
+0000     movs     r0, r0

tests/encode.s

@@ -803,6 +803,20 @@ mcr2    p3, #4, r14, c7, c1, #7
 mcr2    p15, #7, r7, c15, c7, #3
 mcr2    p2, #1, r6, c2, c15
 
+// MCRR
+// T1
+mcrr    p0, #0, r1, r14, c0
+mcrr    p5, #3, r7, r1, c9
+mcrr    p7, #7, r14, r0, c3
+mcrr    p14, #15, r10, r7, c1
+mcrr    p2, #6, r7, r9, c15
+// T2
+mcrr2   p0, #0, r1, r14, c0
+mcrr2   p5, #3, r7, r1, c9
+mcrr2   p7, #7, r14, r0, c3
+mcrr2   p14, #15, r10, r7, c1
+mcrr2   p2, #6, r7, r9, c15
+
 // MLA
 // T1
 mla     r0, r1, r2, r3
@@ -950,6 +964,9 @@ orn     r2, r6, r3, lsl #31
 orns    r7, r0, r14, lsr #10
 orns    r0, r14, r8, asr #5
 
+.org 0x1830
+label_far_s12:
+
 // ORR (immediate)
 // T1
 orr     r0, r1, #0
@@ -973,9 +990,6 @@ orr.w  r7, r10, r14, lsl #31
 orr.w  r3, r0, r7, lsr #7
 orrs.w  r3, r0, r7, asl #3
 
-.org 0x1830
-label_far_s12:
-
 // POP
 // T1
 pop.n   {r0}