Added support for PLD instruction

Author: kingofpayne

src/decoder.rs

@@ -373,6 +373,9 @@ impl BasicInstructionDecoder {
         dec.insert::<instructions::orr::OrrImm>(version);
         dec.insert::<instructions::orr::OrrReg>(version);
         dec.insert::<instructions::pop::Pop>(version);
+        dec.insert::<instructions::pld::PldImm>(version);
+        dec.insert::<instructions::pld::PldLit>(version);
+        dec.insert::<instructions::pld::PldReg>(version);
         dec.insert::<instructions::push::Push>(version);
         dec.insert::<instructions::pssbb::Pssbb>(version);
         dec.insert::<instructions::qadd16::Qadd16>(version);

src/instructions/ldrb.rs

@@ -166,6 +166,7 @@ impl Instruction for LdrbReg {
                 let rm = ins.reg4(0);
                 let rt = ins.reg4(12);
                 let rn = ins.reg4(16);
+                other(rt.is_pc())?; // PLD
                 other(rn.is_pc())?; // LDR (literal)
                 unpredictable(rm.is_sp_or_pc())?;
                 unpredictable(rt.is_pc() && state.in_it_block_not_last())?;

src/instructions/mod.rs

@@ -75,6 +75,7 @@ pub mod mvn;
 pub mod nop;
 pub mod orn;
 pub mod orr;
+pub mod pld;
 pub mod pop;
 pub mod pssbb;
 pub mod push;

src/instructions/pld.rs

@@ -0,0 +1,178 @@
+//! Implements PLD (Preload Data) instructions.
+//!
+//! Emulation of this instruction has no effect and is similar to NOP instruction.
+
+use super::{
+    Encoding::{self, T1, T2},
+    Pattern,
+};
+use crate::{
+    arith::Shift,
+    core::{
+        ArmVersion::{V7EM, V7M, V8M},
+        Effect, ItState, Processor, RunError,
+    },
+    decoder::DecodeError,
+    helpers::BitAccess,
+    instructions::{indexing_args, other, unpredictable, DecodeHelper, Instruction},
+    registers::RegisterIndex,
+};
+
+/// PLD (immediate) instruction.
+///
+/// Preload Data.
+pub struct PldImm {
+    /// Base register.
+    rn: RegisterIndex,
+    /// True to add offset, false to subtract.
+    add: bool,
+    /// Immediate offset applied to Rn.
+    imm32: u32,
+    /// Encoding.
+    encoding: Encoding,
+}
+
+impl Instruction for PldImm {
+    fn patterns() -> &'static [Pattern] {
+        &[
+            Pattern {
+                encoding: T1,
+                versions: &[V7M, V7EM, V8M],
+                expression: "111110001001xxxx1111xxxxxxxxxxxx",
+            },
+            Pattern {
+                encoding: T2,
+                versions: &[V7M, V7EM, V8M],
+                expression: "111110000001xxxx11111100xxxxxxxx",
+            },
+        ]
+    }
+
+    fn try_decode(encoding: Encoding, ins: u32, _state: ItState) -> Result<Self, DecodeError> {
+        let rn = ins.reg4(16);
+        other(rn.is_pc())?; // PLD (literal)
+        Ok(match encoding {
+            T1 => Self {
+                rn,
+                add: true,
+                imm32: ins.imm12(0),
+                encoding,
+            },
+            T2 => Self {
+                rn,
+                add: false,
+                imm32: ins.imm8(0),
+                encoding,
+            },
+            _ => panic!(),
+        })
+    }
+
+    fn execute(&self, _proc: &mut Processor) -> Result<Effect, RunError> {
+        Ok(Effect::None)
+    }
+
+    fn name(&self) -> String {
+        "pld".into()
+    }
+
+    fn args(&self, _pc: u32) -> String {
+        // #0 and #-0 offsets generate different instructions. Therefore for encoding T2 we want
+        // the sign to be explicit.
+        indexing_args(
+            self.rn,
+            self.imm32,
+            self.encoding == T2,
+            true,
+            self.add,
+            false,
+        )
+    }
+}
+
+/// PLD (literal) instruction.
+///
+/// Preload Data.
+pub struct PldLit {
+    /// Label offset.
+    imm32: u32,
+    /// True to add offset, false to subtract.
+    add: bool,
+}
+
+impl Instruction for PldLit {
+    fn patterns() -> &'static [Pattern] {
+        &[Pattern {
+            encoding: T1,
+            versions: &[V7M, V7EM, V8M],
+            expression: "11111000x00111111111xxxxxxxxxxxx",
+        }]
+    }
+
+    fn try_decode(encoding: Encoding, ins: u32, _state: ItState) -> Result<Self, DecodeError> {
+        debug_assert_eq!(encoding, T1);
+        Ok(Self {
+            imm32: ins.imm12(0),
+            add: ins.bit(23),
+        })
+    }
+
+    fn execute(&self, _proc: &mut Processor) -> Result<Effect, RunError> {
+        Ok(Effect::None)
+    }
+
+    fn name(&self) -> String {
+        "pld".into()
+    }
+
+    fn args(&self, _pc: u32) -> String {
+        indexing_args(RegisterIndex::Pc, self.imm32, true, true, self.add, false)
+    }
+}
+
+/// PLD (register) instruction.
+///
+/// Preload Data.
+pub struct PldReg {
+    /// Base register.
+    rn: RegisterIndex,
+    /// Offset register.
+    rm: RegisterIndex,
+    /// Shift to be applied to Rm.
+    shift: Shift,
+}
+
+impl Instruction for PldReg {
+    fn patterns() -> &'static [Pattern] {
+        &[Pattern {
+            encoding: T1,
+            versions: &[V7M, V7EM, V8M],
+            expression: "111110000001xxxx1111000000xxxxxx",
+        }]
+    }
+
+    fn try_decode(encoding: Encoding, ins: u32, _state: ItState) -> Result<Self, DecodeError> {
+        debug_assert_eq!(encoding, T1);
+        let rn = ins.reg4(16);
+        let rm = ins.reg4(0);
+        other(rn.is_pc())?; // PLD (literal)
+        unpredictable(rm.is_sp_or_pc())?;
+        Ok(Self {
+            rn,
+            rm,
+            shift: Shift::lsl(ins.imm2(4)),
+        })
+    }
+
+    fn execute(&self, _proc: &mut Processor) -> Result<Effect, RunError> {
+        Ok(Effect::None)
+    }
+
+    fn name(&self) -> String {
+        "pld".into()
+    }
+
+    fn args(&self, _pc: u32) -> String {
+        format!("[{}, {}{}]", self.rn, self.rm, self.shift.arg_string())
+    }
+}

src/test_decoder.txt

@@ -665,6 +665,26 @@ aff30080 nop.w
 4aeace77 orr.w    r7, r10, lr, lsl #31
 40ead713 orr.w    r3, r0, r7, lsr #7
 50eac703 orrs.w   r3, r0, r7, lsl #3
+90f800f0 pld      [r0]
+93f8aaf0 pld      [r3, #170]
+97f8ffff pld      [r7, #4095]
+9cf828f0 pld      [r12, #40]
+9ef8c4f9 pld      [lr, #2500]
+10f800fc pld      [r0, #-0]
+13f8aafc pld      [r3, #-170]
+17f8fffc pld      [r7, #-255]
+1cf828fc pld      [r12, #-40]
+1ef811fc pld      [lr, #-17]
+9ff800f0 pld      [pc, #0]
+1ff8ffff pld      [pc, #-4095]
+9ff8ffff pld      [pc, #4095]
+9ff8e3f9 pld      [pc, #2531]
+1ff8f1f6 pld      [pc, #-1777]
+10f801f0 pld      [r0, r1]
+13f837f0 pld      [r3, r7, lsl #3]
+1ef81cf0 pld      [lr, r12, lsl #1]
+17f80ef0 pld      [r7, lr]
+12f809f0 pld      [r2, r9]
 01bc     pop      {r0}
 03bc     pop      {r0, r1}
 3abc     pop      {r1, r3, r4, r5}

tests/encode.s

@@ -1073,6 +1073,35 @@ orr.w  r7, r10, r14, lsl #31
 orr.w  r3, r0, r7, lsr #7
 orrs.w  r3, r0, r7, asl #3
 
+// PLD (immediate)
+// T1
+pld     [r0, #0]
+pld     [r3, #170]
+pld     [r7, #4095]
+pld     [r12, #40]
+pld     [r14, #2500]
+// T2
+pld     [r0, #-0]
+pld     [r3, #-170]
+pld     [r7, #-255]
+pld     [r12, #-40]
+pld     [r14, #-17]
+
+// PLD (literal)
+// T1
+pld     [pc]
+pld     [pc, #-4095]
+pld     [pc, #4095]
+pld     [pc, #2531]
+pld     [pc, #-1777]
+
+// PLD (register)
+pld     [r0, r1]
+pld     [r3, r7, lsl #3]
+pld     [r14, r12, lsl #1]
+pld     [r7, r14]
+pld     [r2, r9]
+
 // POP
 // T1
 pop.n   {r0}