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disasm-aarch32.h
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2731 lines (2070 loc) · 81.3 KB
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// Copyright 2017, VIXL authors
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// * Neither the name of ARM Limited nor the names of its contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#ifndef VIXL_DISASM_AARCH32_H_
#define VIXL_DISASM_AARCH32_H_
extern "C" {
#include <stdint.h>
}
#include <iomanip>
#include "aarch32/constants-aarch32.h"
#include "aarch32/operands-aarch32.h"
namespace vixl {
namespace aarch32 {
class ITBlock {
Condition first_condition_;
Condition condition_;
uint16_t it_mask_;
public:
ITBlock() : first_condition_(al), condition_(al), it_mask_(0) {}
void Advance() {
condition_ = Condition((condition_.GetCondition() & 0xe) | (it_mask_ >> 3));
it_mask_ = (it_mask_ << 1) & 0xf;
}
bool InITBlock() const { return it_mask_ != 0; }
bool OutsideITBlock() const { return !InITBlock(); }
bool LastInITBlock() const { return it_mask_ == 0x8; }
bool OutsideITBlockOrLast() const {
return OutsideITBlock() || LastInITBlock();
}
void Set(Condition first_condition, uint16_t mask) {
condition_ = first_condition_ = first_condition;
it_mask_ = mask;
}
Condition GetFirstCondition() const { return first_condition_; }
Condition GetCurrentCondition() const { return condition_; }
};
class Disassembler {
public:
enum LocationType {
kAnyLocation,
kCodeLocation,
kDataLocation,
kCoprocLocation,
kLoadByteLocation,
kLoadHalfWordLocation,
kLoadWordLocation,
kLoadDoubleWordLocation,
kLoadSignedByteLocation,
kLoadSignedHalfWordLocation,
kLoadSinglePrecisionLocation,
kLoadDoublePrecisionLocation,
kStoreByteLocation,
kStoreHalfWordLocation,
kStoreWordLocation,
kStoreDoubleWordLocation,
kStoreSinglePrecisionLocation,
kStoreDoublePrecisionLocation,
kVld1Location,
kVld2Location,
kVld3Location,
kVld4Location,
kVst1Location,
kVst2Location,
kVst3Location,
kVst4Location
};
class ConditionPrinter {
const ITBlock& it_block_;
Condition cond_;
public:
ConditionPrinter(const ITBlock& it_block, Condition cond)
: it_block_(it_block), cond_(cond) {}
const ITBlock& GetITBlock() const { return it_block_; }
Condition GetCond() const { return cond_; }
friend std::ostream& operator<<(std::ostream& os, ConditionPrinter cond) {
if (cond.it_block_.InITBlock() && cond.cond_.Is(al) &&
!cond.cond_.IsNone()) {
return os << "al";
}
return os << cond.cond_;
}
};
class ImmediatePrinter {
uint32_t imm_;
public:
explicit ImmediatePrinter(uint32_t imm) : imm_(imm) {}
uint32_t GetImm() const { return imm_; }
friend std::ostream& operator<<(std::ostream& os, ImmediatePrinter imm) {
return os << "#" << imm.GetImm();
}
};
class SignedImmediatePrinter {
int32_t imm_;
public:
explicit SignedImmediatePrinter(int32_t imm) : imm_(imm) {}
int32_t GetImm() const { return imm_; }
friend std::ostream& operator<<(std::ostream& os,
SignedImmediatePrinter imm) {
return os << "#" << imm.GetImm();
}
};
class RawImmediatePrinter {
uint32_t imm_;
public:
explicit RawImmediatePrinter(uint32_t imm) : imm_(imm) {}
uint32_t GetImm() const { return imm_; }
friend std::ostream& operator<<(std::ostream& os, RawImmediatePrinter imm) {
return os << imm.GetImm();
}
};
class DtPrinter {
DataType dt_;
DataType default_dt_;
public:
DtPrinter(DataType dt, DataType default_dt)
: dt_(dt), default_dt_(default_dt) {}
DataType GetDt() const { return dt_; }
DataType GetDefaultDt() const { return default_dt_; }
friend std::ostream& operator<<(std::ostream& os, DtPrinter dt) {
if (dt.dt_.Is(dt.default_dt_)) return os;
return os << dt.dt_;
}
};
class IndexedRegisterPrinter {
DRegister reg_;
uint32_t index_;
public:
IndexedRegisterPrinter(DRegister reg, uint32_t index)
: reg_(reg), index_(index) {}
DRegister GetReg() const { return reg_; }
uint32_t GetIndex() const { return index_; }
friend std::ostream& operator<<(std::ostream& os,
IndexedRegisterPrinter reg) {
return os << reg.GetReg() << "[" << reg.GetIndex() << "]";
}
};
// TODO: Merge this class with PrintLabel below. This Location class
// represents a PC-relative offset, not an address.
class Location {
public:
typedef int32_t Offset;
Location(Offset immediate, Offset pc_offset)
: immediate_(immediate), pc_offset_(pc_offset) {}
Offset GetImmediate() const { return immediate_; }
Offset GetPCOffset() const { return pc_offset_; }
private:
Offset immediate_;
Offset pc_offset_;
};
class PrintLabel {
LocationType location_type_;
Location::Offset immediate_;
Location::Offset location_;
public:
PrintLabel(LocationType location_type,
Location* offset,
Location::Offset position)
: location_type_(location_type),
immediate_(offset->GetImmediate()),
location_(static_cast<Location::Offset>(
static_cast<int64_t>(offset->GetPCOffset()) +
offset->GetImmediate() + position)) {}
LocationType GetLocationType() const { return location_type_; }
Location::Offset GetLocation() const { return location_; }
Location::Offset GetImmediate() const { return immediate_; }
friend inline std::ostream& operator<<(std::ostream& os,
const PrintLabel& label) {
os << "0x" << std::hex << std::setw(8) << std::setfill('0')
<< label.GetLocation() << std::dec;
return os;
}
};
class PrintMemOperand {
LocationType location_type_;
const MemOperand& operand_;
public:
PrintMemOperand(LocationType location_type, const MemOperand& operand)
: location_type_(location_type), operand_(operand) {}
LocationType GetLocationType() const { return location_type_; }
const MemOperand& GetOperand() const { return operand_; }
};
class PrintAlignedMemOperand {
LocationType location_type_;
const AlignedMemOperand& operand_;
public:
PrintAlignedMemOperand(LocationType location_type,
const AlignedMemOperand& operand)
: location_type_(location_type), operand_(operand) {}
LocationType GetLocationType() const { return location_type_; }
const AlignedMemOperand& GetOperand() const { return operand_; }
};
class DisassemblerStream {
std::ostream& os_;
InstructionType current_instruction_type_;
InstructionAttribute current_instruction_attributes_;
public:
explicit DisassemblerStream(std::ostream& os) // NOLINT(runtime/references)
: os_(os),
current_instruction_type_(kUndefInstructionType),
current_instruction_attributes_(kNoAttribute) {}
virtual ~DisassemblerStream() {}
std::ostream& os() const { return os_; }
void SetCurrentInstruction(
InstructionType current_instruction_type,
InstructionAttribute current_instruction_attributes) {
current_instruction_type_ = current_instruction_type;
current_instruction_attributes_ = current_instruction_attributes;
}
InstructionType GetCurrentInstructionType() const {
return current_instruction_type_;
}
InstructionAttribute GetCurrentInstructionAttributes() const {
return current_instruction_attributes_;
}
bool Has(InstructionAttribute attributes) const {
return (current_instruction_attributes_ & attributes) == attributes;
}
template <typename T>
DisassemblerStream& operator<<(T value) {
os_ << value;
return *this;
}
virtual DisassemblerStream& operator<<(const char* string) {
os_ << string;
return *this;
}
virtual DisassemblerStream& operator<<(const ConditionPrinter& cond) {
os_ << cond;
return *this;
}
virtual DisassemblerStream& operator<<(Condition cond) {
os_ << cond;
return *this;
}
virtual DisassemblerStream& operator<<(const EncodingSize& size) {
os_ << size;
return *this;
}
virtual DisassemblerStream& operator<<(const ImmediatePrinter& imm) {
os_ << imm;
return *this;
}
virtual DisassemblerStream& operator<<(const SignedImmediatePrinter& imm) {
os_ << imm;
return *this;
}
virtual DisassemblerStream& operator<<(const RawImmediatePrinter& imm) {
os_ << imm;
return *this;
}
virtual DisassemblerStream& operator<<(const DtPrinter& dt) {
os_ << dt;
return *this;
}
virtual DisassemblerStream& operator<<(const DataType& type) {
os_ << type;
return *this;
}
virtual DisassemblerStream& operator<<(Shift shift) {
os_ << shift;
return *this;
}
virtual DisassemblerStream& operator<<(Sign sign) {
os_ << sign;
return *this;
}
virtual DisassemblerStream& operator<<(Alignment alignment) {
os_ << alignment;
return *this;
}
virtual DisassemblerStream& operator<<(const PrintLabel& label) {
os_ << label;
return *this;
}
virtual DisassemblerStream& operator<<(const WriteBack& write_back) {
os_ << write_back;
return *this;
}
virtual DisassemblerStream& operator<<(const NeonImmediate& immediate) {
os_ << immediate;
return *this;
}
virtual DisassemblerStream& operator<<(Register reg) {
os_ << reg;
return *this;
}
virtual DisassemblerStream& operator<<(SRegister reg) {
os_ << reg;
return *this;
}
virtual DisassemblerStream& operator<<(DRegister reg) {
os_ << reg;
return *this;
}
virtual DisassemblerStream& operator<<(QRegister reg) {
os_ << reg;
return *this;
}
virtual DisassemblerStream& operator<<(const RegisterOrAPSR_nzcv reg) {
os_ << reg;
return *this;
}
virtual DisassemblerStream& operator<<(SpecialRegister reg) {
os_ << reg;
return *this;
}
virtual DisassemblerStream& operator<<(MaskedSpecialRegister reg) {
os_ << reg;
return *this;
}
virtual DisassemblerStream& operator<<(SpecialFPRegister reg) {
os_ << reg;
return *this;
}
virtual DisassemblerStream& operator<<(BankedRegister reg) {
os_ << reg;
return *this;
}
virtual DisassemblerStream& operator<<(const RegisterList& list) {
os_ << list;
return *this;
}
virtual DisassemblerStream& operator<<(const SRegisterList& list) {
os_ << list;
return *this;
}
virtual DisassemblerStream& operator<<(const DRegisterList& list) {
os_ << list;
return *this;
}
virtual DisassemblerStream& operator<<(const NeonRegisterList& list) {
os_ << list;
return *this;
}
virtual DisassemblerStream& operator<<(const DRegisterLane& reg) {
os_ << reg;
return *this;
}
virtual DisassemblerStream& operator<<(const IndexedRegisterPrinter& reg) {
os_ << reg;
return *this;
}
virtual DisassemblerStream& operator<<(Coprocessor coproc) {
os_ << coproc;
return *this;
}
virtual DisassemblerStream& operator<<(CRegister reg) {
os_ << reg;
return *this;
}
virtual DisassemblerStream& operator<<(Endianness endian_specifier) {
os_ << endian_specifier;
return *this;
}
virtual DisassemblerStream& operator<<(MemoryBarrier option) {
os_ << option;
return *this;
}
virtual DisassemblerStream& operator<<(InterruptFlags iflags) {
os_ << iflags;
return *this;
}
virtual DisassemblerStream& operator<<(const Operand& operand) {
if (operand.IsImmediate()) {
if (Has(kBitwise)) {
return *this << "#0x" << std::hex << operand.GetImmediate()
<< std::dec;
}
return *this << "#" << operand.GetImmediate();
}
if (operand.IsImmediateShiftedRegister()) {
if ((operand.GetShift().IsLSL() || operand.GetShift().IsROR()) &&
(operand.GetShiftAmount() == 0)) {
return *this << operand.GetBaseRegister();
}
if (operand.GetShift().IsRRX()) {
return *this << operand.GetBaseRegister() << ", rrx";
}
return *this << operand.GetBaseRegister() << ", " << operand.GetShift()
<< " #" << operand.GetShiftAmount();
}
if (operand.IsRegisterShiftedRegister()) {
return *this << operand.GetBaseRegister() << ", " << operand.GetShift()
<< " " << operand.GetShiftRegister();
}
VIXL_UNREACHABLE();
return *this;
}
virtual DisassemblerStream& operator<<(const SOperand& operand) {
if (operand.IsImmediate()) {
return *this << operand.GetNeonImmediate();
}
return *this << operand.GetRegister();
}
virtual DisassemblerStream& operator<<(const DOperand& operand) {
if (operand.IsImmediate()) {
return *this << operand.GetNeonImmediate();
}
return *this << operand.GetRegister();
}
virtual DisassemblerStream& operator<<(const QOperand& operand) {
if (operand.IsImmediate()) {
return *this << operand.GetNeonImmediate();
}
return *this << operand.GetRegister();
}
virtual DisassemblerStream& operator<<(const MemOperand& operand) {
*this << "[" << operand.GetBaseRegister();
if (operand.GetAddrMode() == PostIndex) {
*this << "]";
if (operand.IsRegisterOnly()) return *this << "!";
}
if (operand.IsImmediate()) {
if ((operand.GetOffsetImmediate() != 0) ||
operand.GetSign().IsMinus() ||
((operand.GetAddrMode() != Offset) && !operand.IsRegisterOnly())) {
if (operand.GetOffsetImmediate() == 0) {
*this << ", #" << operand.GetSign() << operand.GetOffsetImmediate();
} else {
*this << ", #" << operand.GetOffsetImmediate();
}
}
} else if (operand.IsPlainRegister()) {
*this << ", " << operand.GetSign() << operand.GetOffsetRegister();
} else if (operand.IsShiftedRegister()) {
*this << ", " << operand.GetSign() << operand.GetOffsetRegister()
<< ImmediateShiftOperand(operand.GetShift(),
operand.GetShiftAmount());
} else {
VIXL_UNREACHABLE();
return *this;
}
if (operand.GetAddrMode() == Offset) {
*this << "]";
} else if (operand.GetAddrMode() == PreIndex) {
*this << "]!";
}
return *this;
}
virtual DisassemblerStream& operator<<(const PrintMemOperand& operand) {
return *this << operand.GetOperand();
}
virtual DisassemblerStream& operator<<(const AlignedMemOperand& operand) {
*this << "[" << operand.GetBaseRegister() << operand.GetAlignment()
<< "]";
if (operand.GetAddrMode() == PostIndex) {
if (operand.IsPlainRegister()) {
*this << ", " << operand.GetOffsetRegister();
} else {
*this << "!";
}
}
return *this;
}
virtual DisassemblerStream& operator<<(
const PrintAlignedMemOperand& operand) {
return *this << operand.GetOperand();
}
};
private:
class ITBlockScope {
ITBlock* const it_block_;
bool inside_;
public:
explicit ITBlockScope(ITBlock* it_block)
: it_block_(it_block), inside_(it_block->InITBlock()) {}
~ITBlockScope() {
if (inside_) it_block_->Advance();
}
};
ITBlock it_block_;
DisassemblerStream* os_;
bool owns_os_;
uint32_t code_address_;
// True if the disassembler always output instructions with all the
// registers (even if two registers are identical and only one could be
// output).
bool use_short_hand_form_;
public:
explicit Disassembler(std::ostream& os, // NOLINT(runtime/references)
uint32_t code_address = 0)
: os_(new DisassemblerStream(os)),
owns_os_(true),
code_address_(code_address),
use_short_hand_form_(true) {}
explicit Disassembler(DisassemblerStream* os, uint32_t code_address = 0)
: os_(os),
owns_os_(false),
code_address_(code_address),
use_short_hand_form_(true) {}
virtual ~Disassembler() {
if (owns_os_) {
delete os_;
}
}
DisassemblerStream& os() const { return *os_; }
void SetIT(Condition first_condition, uint16_t it_mask) {
it_block_.Set(first_condition, it_mask);
}
const ITBlock& GetITBlock() const { return it_block_; }
bool InITBlock() const { return it_block_.InITBlock(); }
bool OutsideITBlock() const { return it_block_.OutsideITBlock(); }
bool OutsideITBlockOrLast() const { return it_block_.OutsideITBlockOrLast(); }
void CheckNotIT() const { VIXL_ASSERT(it_block_.OutsideITBlock()); }
// Return the current condition depending on the IT state for T32.
Condition CurrentCond() const {
if (it_block_.OutsideITBlock()) return al;
return it_block_.GetCurrentCondition();
}
bool UseShortHandForm() const { return use_short_hand_form_; }
void SetUseShortHandForm(bool use_short_hand_form) {
use_short_hand_form_ = use_short_hand_form;
}
virtual void UnallocatedT32(uint32_t instruction) {
if (T32Size(instruction) == 2) {
os() << "unallocated " << std::hex << std::setw(4) << std::setfill('0')
<< (instruction >> 16) << std::dec;
} else {
os() << "unallocated " << std::hex << std::setw(8) << std::setfill('0')
<< instruction << std::dec;
}
}
virtual void UnallocatedA32(uint32_t instruction) {
os() << "unallocated " << std::hex << std::setw(8) << std::setfill('0')
<< instruction << std::dec;
}
virtual void UnimplementedT32_16(const char* name, uint32_t instruction) {
os() << "unimplemented " << name << " T32:" << std::hex << std::setw(4)
<< std::setfill('0') << (instruction >> 16) << std::dec;
}
virtual void UnimplementedT32_32(const char* name, uint32_t instruction) {
os() << "unimplemented " << name << " T32:" << std::hex << std::setw(8)
<< std::setfill('0') << instruction << std::dec;
}
virtual void UnimplementedA32(const char* name, uint32_t instruction) {
os() << "unimplemented " << name << " ARM:" << std::hex << std::setw(8)
<< std::setfill('0') << instruction << std::dec;
}
virtual void Unpredictable() { os() << " ; unpredictable"; }
virtual void UnpredictableT32(uint32_t /*instr*/) { return Unpredictable(); }
virtual void UnpredictableA32(uint32_t /*instr*/) { return Unpredictable(); }
static bool Is16BitEncoding(uint32_t instr) { return instr < 0xe8000000; }
uint32_t GetCodeAddress() const { return code_address_; }
void SetCodeAddress(uint32_t code_address) { code_address_ = code_address; }
// Start of generated code.
void adc(Condition cond,
EncodingSize size,
Register rd,
Register rn,
const Operand& operand);
void adcs(Condition cond,
EncodingSize size,
Register rd,
Register rn,
const Operand& operand);
void add(Condition cond,
EncodingSize size,
Register rd,
Register rn,
const Operand& operand);
void add(Condition cond, Register rd, const Operand& operand);
void adds(Condition cond,
EncodingSize size,
Register rd,
Register rn,
const Operand& operand);
void adds(Register rd, const Operand& operand);
void addw(Condition cond, Register rd, Register rn, const Operand& operand);
void adr(Condition cond, EncodingSize size, Register rd, Location* location);
void aesd(Condition cond, DataType dt, QRegister rd, QRegister rm);
void aese(Condition cond, DataType dt, QRegister rd, QRegister rm);
void aesimc(Condition cond, DataType dt, QRegister rd, QRegister rm);
void aesmc(Condition cond, DataType dt, QRegister rd, QRegister rm);
void and_(Condition cond,
EncodingSize size,
Register rd,
Register rn,
const Operand& operand);
void ands(Condition cond,
EncodingSize size,
Register rd,
Register rn,
const Operand& operand);
void asr(Condition cond,
EncodingSize size,
Register rd,
Register rm,
const Operand& operand);
void asrs(Condition cond,
EncodingSize size,
Register rd,
Register rm,
const Operand& operand);
void b(Condition cond, EncodingSize size, Location* location);
void bfc(Condition cond, Register rd, uint32_t lsb, uint32_t width);
void bfi(
Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width);
void bic(Condition cond,
EncodingSize size,
Register rd,
Register rn,
const Operand& operand);
void bics(Condition cond,
EncodingSize size,
Register rd,
Register rn,
const Operand& operand);
void bkpt(Condition cond, uint32_t imm);
void bl(Condition cond, Location* location);
void blx(Condition cond, Location* location);
void blx(Condition cond, Register rm);
void bx(Condition cond, Register rm);
void bxj(Condition cond, Register rm);
void cbnz(Register rn, Location* location);
void cbz(Register rn, Location* location);
void clrex(Condition cond);
void clz(Condition cond, Register rd, Register rm);
void cmn(Condition cond,
EncodingSize size,
Register rn,
const Operand& operand);
void cmp(Condition cond,
EncodingSize size,
Register rn,
const Operand& operand);
void crc32b(Condition cond, Register rd, Register rn, Register rm);
void crc32cb(Condition cond, Register rd, Register rn, Register rm);
void crc32ch(Condition cond, Register rd, Register rn, Register rm);
void crc32cw(Condition cond, Register rd, Register rn, Register rm);
void crc32h(Condition cond, Register rd, Register rn, Register rm);
void crc32w(Condition cond, Register rd, Register rn, Register rm);
void dmb(Condition cond, MemoryBarrier option);
void dsb(Condition cond, MemoryBarrier option);
void eor(Condition cond,
EncodingSize size,
Register rd,
Register rn,
const Operand& operand);
void eors(Condition cond,
EncodingSize size,
Register rd,
Register rn,
const Operand& operand);
void fldmdbx(Condition cond,
Register rn,
WriteBack write_back,
DRegisterList dreglist);
void fldmiax(Condition cond,
Register rn,
WriteBack write_back,
DRegisterList dreglist);
void fstmdbx(Condition cond,
Register rn,
WriteBack write_back,
DRegisterList dreglist);
void fstmiax(Condition cond,
Register rn,
WriteBack write_back,
DRegisterList dreglist);
void hlt(Condition cond, uint32_t imm);
void hvc(Condition cond, uint32_t imm);
void isb(Condition cond, MemoryBarrier option);
void it(Condition cond, uint16_t mask);
void lda(Condition cond, Register rt, const MemOperand& operand);
void ldab(Condition cond, Register rt, const MemOperand& operand);
void ldaex(Condition cond, Register rt, const MemOperand& operand);
void ldaexb(Condition cond, Register rt, const MemOperand& operand);
void ldaexd(Condition cond,
Register rt,
Register rt2,
const MemOperand& operand);
void ldaexh(Condition cond, Register rt, const MemOperand& operand);
void ldah(Condition cond, Register rt, const MemOperand& operand);
void ldm(Condition cond,
EncodingSize size,
Register rn,
WriteBack write_back,
RegisterList registers);
void ldmda(Condition cond,
Register rn,
WriteBack write_back,
RegisterList registers);
void ldmdb(Condition cond,
Register rn,
WriteBack write_back,
RegisterList registers);
void ldmea(Condition cond,
Register rn,
WriteBack write_back,
RegisterList registers);
void ldmed(Condition cond,
Register rn,
WriteBack write_back,
RegisterList registers);
void ldmfa(Condition cond,
Register rn,
WriteBack write_back,
RegisterList registers);
void ldmfd(Condition cond,
EncodingSize size,
Register rn,
WriteBack write_back,
RegisterList registers);
void ldmib(Condition cond,
Register rn,
WriteBack write_back,
RegisterList registers);
void ldr(Condition cond,
EncodingSize size,
Register rt,
const MemOperand& operand);
void ldr(Condition cond, EncodingSize size, Register rt, Location* location);
void ldrb(Condition cond,
EncodingSize size,
Register rt,
const MemOperand& operand);
void ldrb(Condition cond, Register rt, Location* location);
void ldrd(Condition cond,
Register rt,
Register rt2,
const MemOperand& operand);
void ldrd(Condition cond, Register rt, Register rt2, Location* location);
void ldrex(Condition cond, Register rt, const MemOperand& operand);
void ldrexb(Condition cond, Register rt, const MemOperand& operand);
void ldrexd(Condition cond,
Register rt,
Register rt2,
const MemOperand& operand);
void ldrexh(Condition cond, Register rt, const MemOperand& operand);
void ldrh(Condition cond,
EncodingSize size,
Register rt,
const MemOperand& operand);
void ldrh(Condition cond, Register rt, Location* location);
void ldrsb(Condition cond,
EncodingSize size,
Register rt,
const MemOperand& operand);
void ldrsb(Condition cond, Register rt, Location* location);
void ldrsh(Condition cond,
EncodingSize size,
Register rt,
const MemOperand& operand);
void ldrsh(Condition cond, Register rt, Location* location);
void lsl(Condition cond,
EncodingSize size,
Register rd,
Register rm,
const Operand& operand);
void lsls(Condition cond,
EncodingSize size,
Register rd,
Register rm,
const Operand& operand);
void lsr(Condition cond,
EncodingSize size,
Register rd,
Register rm,
const Operand& operand);
void lsrs(Condition cond,
EncodingSize size,
Register rd,
Register rm,
const Operand& operand);
void mla(Condition cond, Register rd, Register rn, Register rm, Register ra);
void mlas(Condition cond, Register rd, Register rn, Register rm, Register ra);
void mls(Condition cond, Register rd, Register rn, Register rm, Register ra);
void mov(Condition cond,
EncodingSize size,
Register rd,
const Operand& operand);
void movs(Condition cond,
EncodingSize size,
Register rd,
const Operand& operand);
void movt(Condition cond, Register rd, const Operand& operand);
void movw(Condition cond, Register rd, const Operand& operand);
void mrs(Condition cond, Register rd, SpecialRegister spec_reg);
void msr(Condition cond,
MaskedSpecialRegister spec_reg,
const Operand& operand);
void mul(
Condition cond, EncodingSize size, Register rd, Register rn, Register rm);
void muls(Condition cond, Register rd, Register rn, Register rm);
void mvn(Condition cond,
EncodingSize size,
Register rd,
const Operand& operand);
void mvns(Condition cond,
EncodingSize size,
Register rd,
const Operand& operand);
void nop(Condition cond, EncodingSize size);
void orn(Condition cond, Register rd, Register rn, const Operand& operand);
void orns(Condition cond, Register rd, Register rn, const Operand& operand);
void orr(Condition cond,
EncodingSize size,
Register rd,
Register rn,
const Operand& operand);
void orrs(Condition cond,
EncodingSize size,
Register rd,
Register rn,
const Operand& operand);
void pkhbt(Condition cond, Register rd, Register rn, const Operand& operand);
void pkhtb(Condition cond, Register rd, Register rn, const Operand& operand);
void pld(Condition cond, Location* location);
void pld(Condition cond, const MemOperand& operand);
void pldw(Condition cond, const MemOperand& operand);
void pli(Condition cond, const MemOperand& operand);
void pli(Condition cond, Location* location);
void pop(Condition cond, EncodingSize size, RegisterList registers);
void pop(Condition cond, EncodingSize size, Register rt);
void push(Condition cond, EncodingSize size, RegisterList registers);
void push(Condition cond, EncodingSize size, Register rt);
void qadd(Condition cond, Register rd, Register rm, Register rn);
void qadd16(Condition cond, Register rd, Register rn, Register rm);
void qadd8(Condition cond, Register rd, Register rn, Register rm);