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simulator-aarch64.h
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5166 lines (4660 loc) · 193 KB
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// Copyright 2015, VIXL authors
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// * Neither the name of ARM Limited nor the names of its contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#ifndef VIXL_AARCH64_SIMULATOR_AARCH64_H_
#define VIXL_AARCH64_SIMULATOR_AARCH64_H_
#include <memory>
#include <unordered_map>
#include <unordered_set>
#include <vector>
#include "../globals-vixl.h"
#include "../utils-vixl.h"
#include "cpu-features.h"
#include "abi-aarch64.h"
#include "cpu-features-auditor-aarch64.h"
#include "disasm-aarch64.h"
#include "instructions-aarch64.h"
#include "simulator-constants-aarch64.h"
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
// These are only used for the ABI feature, and depend on checks performed for
// it.
#ifdef VIXL_HAS_ABI_SUPPORT
#include <tuple>
#if __cplusplus >= 201402L
// Required for `std::index_sequence`
#include <utility>
#endif
#endif
// The hosts that Simulator running on may not have these flags defined.
#ifndef PROT_BTI
#define PROT_BTI 0x10
#endif
#ifndef PROT_MTE
#define PROT_MTE 0x20
#endif
namespace vixl {
namespace aarch64 {
class SimStack {
public:
SimStack() {}
explicit SimStack(size_t size) : usable_size_(size) {}
// Guard against accesses above the stack base. This could occur, for example,
// if the first simulated function tries to read stack arguments that haven't
// been properly initialised in the Simulator's stack.
void SetBaseGuardSize(size_t size) { base_guard_size_ = size; }
// Guard against stack overflows. The size should be large enough to detect
// the largest stride made (by `MacroAssembler::Claim()` or equivalent) whilst
// initialising stack objects.
void SetLimitGuardSize(size_t size) { limit_guard_size_ = size; }
// The minimum usable size of the stack.
// Equal to "stack base" - "stack limit", in AAPCS64 terminology.
void SetUsableSize(size_t size) { usable_size_ = size; }
// Set the minimum alignment for the stack parameters.
void AlignToBytesLog2(int align_log2) { align_log2_ = align_log2; }
class Allocated {
public:
// Using AAPCS64 terminology, highest addresses at the top:
//
// data_.get() + alloc_size ->
// |
// | Base guard
// GetBase() -> | |
// | |
// | | AAPCS64-legal
// | Usable stack | values of 'sp'.
// | |
// | |
// GetLimit() -> |
// | Limit guard
// data_.get() -> |
//
// The Simulator detects (and forbids) accesses to either guard region.
char* GetBase() const { return base_; }
char* GetLimit() const { return limit_; }
template <typename T>
bool IsAccessInGuardRegion(const T* base, size_t size) const {
VIXL_ASSERT(size > 0);
// Inclusive bounds.
const char* start = reinterpret_cast<const char*>(base);
const char* end = start + size - 1;
const char* data_start = data_.get();
const char* data_end = data_start + alloc_size_ - 1;
bool in_base_guard = (start <= data_end) && (end >= base_);
bool in_limit_guard = (start <= limit_) && (end >= data_start);
return in_base_guard || in_limit_guard;
}
private:
std::unique_ptr<char[]> data_;
char* limit_;
char* base_;
size_t alloc_size_;
friend class SimStack;
};
// Allocate the stack, locking the parameters.
Allocated Allocate() {
size_t align_to = 1 << align_log2_;
size_t l = AlignUp(limit_guard_size_, align_to);
size_t u = AlignUp(usable_size_, align_to);
size_t b = AlignUp(base_guard_size_, align_to);
size_t size = l + u + b;
Allocated a;
size_t alloc_size = (align_to - 1) + size;
a.data_ = std::make_unique<char[]>(alloc_size);
void* data = a.data_.get();
auto data_aligned =
reinterpret_cast<char*>(std::align(align_to, size, data, alloc_size));
a.limit_ = data_aligned + l - 1;
a.base_ = data_aligned + l + u;
a.alloc_size_ = alloc_size;
return a;
}
private:
size_t base_guard_size_ = 256;
size_t limit_guard_size_ = 4 * 1024;
size_t usable_size_ = 8 * 1024;
size_t align_log2_ = 4;
static const size_t kDefaultBaseGuardSize = 256;
static const size_t kDefaultLimitGuardSize = 4 * 1024;
static const size_t kDefaultUsableSize = 8 * 1024;
};
// Armv8.5 MTE helpers.
inline int GetAllocationTagFromAddress(uint64_t address) {
return static_cast<int>(ExtractUnsignedBitfield64(59, 56, address));
}
template <typename T>
T AddressUntag(T address) {
// Cast the address using a C-style cast. A reinterpret_cast would be
// appropriate, but it can't cast one integral type to another.
uint64_t bits = (uint64_t)address;
return (T)(bits & ~kAddressTagMask);
}
class MetaDataDepot {
public:
class MetaDataMTE {
public:
explicit MetaDataMTE(int tag) : tag_(tag) {}
int GetTag() const { return tag_; }
void SetTag(int tag) {
VIXL_ASSERT(IsUint4(tag));
tag_ = tag;
}
static bool IsActive() { return is_active; }
static void SetActive(bool value) { is_active = value; }
private:
static bool is_active;
int16_t tag_;
friend class MetaDataDepot;
};
// Generate a key for metadata recording from a untagged address.
template <typename T>
uint64_t GenerateMTEkey(T address) const {
return reinterpret_cast<uint64_t>(AddressUntag(address)) >>
kMTETagGranuleInBytesLog2;
}
template <typename R, typename T>
R GetAttribute(T map, uint64_t key) {
auto pair = map->find(key);
R value = (pair == map->end()) ? nullptr : &pair->second;
return value;
}
template <typename T>
int GetMTETag(T address, Instruction const* pc = nullptr) {
uint64_t key = GenerateMTEkey(address);
MetaDataMTE* m = GetAttribute<MetaDataMTE*>(&metadata_mte_, key);
if (!m) {
std::stringstream sstream;
sstream << std::hex << "MTE ERROR : instruction at 0x"
<< reinterpret_cast<uint64_t>(pc)
<< " touched a unallocated memory location 0x"
<< reinterpret_cast<uint64_t>(address) << ".\n";
VIXL_ABORT_WITH_MSG(sstream.str().c_str());
}
return m->GetTag();
}
template <typename T>
void SetMTETag(T address, int tag, Instruction const* pc = nullptr) {
VIXL_ASSERT(
IsAligned(reinterpret_cast<uintptr_t>(address), kMTETagGranuleInBytes));
uint64_t key = GenerateMTEkey(address);
MetaDataMTE* m = GetAttribute<MetaDataMTE*>(&metadata_mte_, key);
if (!m) {
metadata_mte_.insert({key, MetaDataMTE(tag)});
} else {
// Overwrite
if (m->GetTag() == tag) {
std::stringstream sstream;
sstream << std::hex << "MTE WARNING : instruction at 0x"
<< reinterpret_cast<uint64_t>(pc)
<< ", the same tag is assigned to the address 0x"
<< reinterpret_cast<uint64_t>(address) << ".\n";
VIXL_WARNING(sstream.str().c_str());
}
m->SetTag(tag);
}
}
template <typename T>
size_t CleanMTETag(T address) {
VIXL_ASSERT(
IsAligned(reinterpret_cast<uintptr_t>(address), kMTETagGranuleInBytes));
uint64_t key = GenerateMTEkey(address);
return metadata_mte_.erase(key);
}
size_t GetTotalCountMTE() { return metadata_mte_.size(); }
// BTI
// All addresses within a page share the same key.
uint64_t GenerateBTIKey(uint64_t address) const {
return AddressUntag(address) >> kPageSizeLog2;
}
bool InGuardedPage(uintptr_t address) const {
uint64_t key = GenerateBTIKey(address);
auto m = metadata_bti_.find(key);
// Assume the default page attribute is NOT guarded.
return m != metadata_bti_.end();
}
void ClearBTIGuard(uintptr_t address, size_t length) {
VIXL_ASSERT(IsAligned(address, kPageSize));
VIXL_ASSERT(length % kPageSize == 0);
for (size_t offset = 0; offset < length; offset += kPageSize) {
uint64_t key = GenerateBTIKey(address + offset);
if (metadata_bti_.erase(key)) {
std::stringstream sstream;
sstream << std::hex << "BTI WARNING : The page at 0x" << address
<< " is already unguarded.\n";
}
}
}
void SetBTIGuard(uintptr_t address, size_t length) {
VIXL_ASSERT(IsAligned(address, kPageSize));
VIXL_ASSERT(length % kPageSize == 0);
for (size_t offset = 0; offset < length; offset += kPageSize) {
uint64_t key = GenerateBTIKey(address + offset);
auto m = metadata_bti_.find(key);
if (m == metadata_bti_.end()) {
metadata_bti_.insert(key);
} else {
std::stringstream sstream;
sstream << std::hex << "BTI WARNING : The page at 0x" << address
<< " is already guarded.\n";
}
}
}
private:
// Tag recording of each allocated memory in the tag-granule.
std::unordered_map<uint64_t, class MetaDataMTE> metadata_mte_;
// Recording of BTI-guarded pages.
std::unordered_set<uint64_t> metadata_bti_;
};
// Representation of memory, with typed getters and setters for access.
class Memory {
public:
explicit Memory(SimStack::Allocated stack) : stack_(std::move(stack)) {
metadata_depot_ = nullptr;
}
const SimStack::Allocated& GetStack() { return stack_; }
template <typename A>
bool IsMTETagsMatched(A address, Instruction const* pc = nullptr) const {
if (MetaDataDepot::MetaDataMTE::IsActive()) {
int pointer_tag = GetAllocationTagFromAddress((uint64_t)address);
int memory_tag =
metadata_depot_->GetMTETag((uint64_t)AddressUntag(address), pc);
return pointer_tag == memory_tag;
}
return true;
}
template <typename T, typename A>
T Read(A address, Instruction const* pc = nullptr) const {
T value;
VIXL_STATIC_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) ||
(sizeof(value) == 4) || (sizeof(value) == 8) ||
(sizeof(value) == 16));
auto base = reinterpret_cast<const char*>(AddressUntag(address));
if (stack_.IsAccessInGuardRegion(base, sizeof(value))) {
VIXL_ABORT_WITH_MSG("Attempt to read from stack guard region");
}
if (!IsMTETagsMatched(address, pc)) {
VIXL_ABORT_WITH_MSG("Tag mismatch.");
}
memcpy(&value, base, sizeof(value));
return value;
}
template <typename T, typename A>
void Write(A address, T value, Instruction const* pc = nullptr) const {
VIXL_STATIC_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) ||
(sizeof(value) == 4) || (sizeof(value) == 8) ||
(sizeof(value) == 16));
auto base = reinterpret_cast<char*>(AddressUntag(address));
if (stack_.IsAccessInGuardRegion(base, sizeof(value))) {
VIXL_ABORT_WITH_MSG("Attempt to write to stack guard region");
}
if (!IsMTETagsMatched(address, pc)) {
VIXL_ABORT_WITH_MSG("Tag mismatch.");
}
memcpy(base, &value, sizeof(value));
}
template <typename A>
uint64_t ReadUint(int size_in_bytes, A address) const {
switch (size_in_bytes) {
case 1:
return Read<uint8_t>(address);
case 2:
return Read<uint16_t>(address);
case 4:
return Read<uint32_t>(address);
case 8:
return Read<uint64_t>(address);
}
VIXL_UNREACHABLE();
return 0;
}
template <typename A>
int64_t ReadInt(int size_in_bytes, A address) const {
switch (size_in_bytes) {
case 1:
return Read<int8_t>(address);
case 2:
return Read<int16_t>(address);
case 4:
return Read<int32_t>(address);
case 8:
return Read<int64_t>(address);
}
VIXL_UNREACHABLE();
return 0;
}
template <typename A>
void Write(int size_in_bytes, A address, uint64_t value) const {
switch (size_in_bytes) {
case 1:
return Write(address, static_cast<uint8_t>(value));
case 2:
return Write(address, static_cast<uint16_t>(value));
case 4:
return Write(address, static_cast<uint32_t>(value));
case 8:
return Write(address, value);
}
VIXL_UNREACHABLE();
}
void AppendMetaData(MetaDataDepot* metadata_depot) {
VIXL_ASSERT(metadata_depot != nullptr);
VIXL_ASSERT(metadata_depot_ == nullptr);
metadata_depot_ = metadata_depot;
}
private:
SimStack::Allocated stack_;
MetaDataDepot* metadata_depot_;
};
// Represent a register (r0-r31, v0-v31, z0-z31, p0-p15).
template <unsigned kMaxSizeInBits>
class SimRegisterBase {
public:
static const unsigned kMaxSizeInBytes = kMaxSizeInBits / kBitsPerByte;
VIXL_STATIC_ASSERT((kMaxSizeInBytes * kBitsPerByte) == kMaxSizeInBits);
SimRegisterBase() : size_in_bytes_(kMaxSizeInBytes) { Clear(); }
unsigned GetSizeInBits() const { return size_in_bytes_ * kBitsPerByte; }
unsigned GetSizeInBytes() const { return size_in_bytes_; }
void SetSizeInBytes(unsigned size_in_bytes) {
VIXL_ASSERT(size_in_bytes <= kMaxSizeInBytes);
size_in_bytes_ = size_in_bytes;
}
void SetSizeInBits(unsigned size_in_bits) {
VIXL_ASSERT(size_in_bits <= kMaxSizeInBits);
VIXL_ASSERT((size_in_bits % kBitsPerByte) == 0);
SetSizeInBytes(size_in_bits / kBitsPerByte);
}
// Write the specified value. The value is zero-extended if necessary.
template <typename T>
void Write(T new_value) {
// All AArch64 registers are zero-extending.
if (sizeof(new_value) < GetSizeInBytes()) Clear();
WriteLane(new_value, 0);
NotifyRegisterWrite();
}
template <typename T>
VIXL_DEPRECATED("Write", void Set(T new_value)) {
Write(new_value);
}
void Clear() {
memset(value_, 0, kMaxSizeInBytes);
NotifyRegisterWrite();
}
// Insert a typed value into a register, leaving the rest of the register
// unchanged. The lane parameter indicates where in the register the value
// should be inserted, in the range [ 0, sizeof(value_) / sizeof(T) ), where
// 0 represents the least significant bits.
template <typename T>
void Insert(int lane, T new_value) {
WriteLane(new_value, lane);
NotifyRegisterWrite();
}
// Get the value as the specified type. The value is truncated if necessary.
template <typename T>
T Get() const {
return GetLane<T>(0);
}
// Get the lane value as the specified type. The value is truncated if
// necessary.
template <typename T>
T GetLane(int lane) const {
T result;
ReadLane(&result, lane);
return result;
}
template <typename T>
VIXL_DEPRECATED("GetLane", T Get(int lane) const) {
return GetLane(lane);
}
// Get the value of a specific bit, indexed from the least-significant bit of
// lane 0.
bool GetBit(int bit) const {
int bit_in_byte = bit % (sizeof(value_[0]) * kBitsPerByte);
int byte = bit / (sizeof(value_[0]) * kBitsPerByte);
return ((value_[byte] >> bit_in_byte) & 1) != 0;
}
// Return a pointer to the raw, underlying byte array.
const uint8_t* GetBytes() const { return value_; }
// TODO: Make this return a map of updated bytes, so that we can highlight
// updated lanes for load-and-insert. (That never happens for scalar code, but
// NEON has some instructions that can update individual lanes.)
bool WrittenSinceLastLog() const { return written_since_last_log_; }
void NotifyRegisterLogged() { written_since_last_log_ = false; }
protected:
uint8_t value_[kMaxSizeInBytes];
unsigned size_in_bytes_;
// Helpers to aid with register tracing.
bool written_since_last_log_;
void NotifyRegisterWrite() { written_since_last_log_ = true; }
private:
template <typename T>
void ReadLane(T* dst, int lane) const {
VIXL_ASSERT(lane >= 0);
VIXL_ASSERT((sizeof(*dst) + (lane * sizeof(*dst))) <= GetSizeInBytes());
memcpy(dst, &value_[lane * sizeof(*dst)], sizeof(*dst));
}
template <typename T>
void WriteLane(T src, int lane) {
VIXL_ASSERT(lane >= 0);
VIXL_ASSERT((sizeof(src) + (lane * sizeof(src))) <= GetSizeInBytes());
memcpy(&value_[lane * sizeof(src)], &src, sizeof(src));
}
// The default ReadLane and WriteLane methods assume what we are copying is
// "trivially copyable" by using memcpy. We have to provide alternative
// implementations for SimFloat16 which cannot be copied this way.
void ReadLane(vixl::internal::SimFloat16* dst, int lane) const {
uint16_t rawbits;
ReadLane(&rawbits, lane);
*dst = RawbitsToFloat16(rawbits);
}
void WriteLane(vixl::internal::SimFloat16 src, int lane) {
WriteLane(Float16ToRawbits(src), lane);
}
};
typedef SimRegisterBase<kXRegSize> SimRegister; // r0-r31
typedef SimRegisterBase<kPRegMaxSize> SimPRegister; // p0-p15
// FFR has the same format as a predicate register.
typedef SimPRegister SimFFRRegister;
// v0-v31 and z0-z31
class SimVRegister : public SimRegisterBase<kZRegMaxSize> {
public:
SimVRegister() : SimRegisterBase<kZRegMaxSize>(), accessed_as_z_(false) {}
void NotifyAccessAsZ() { accessed_as_z_ = true; }
void NotifyRegisterLogged() {
SimRegisterBase<kZRegMaxSize>::NotifyRegisterLogged();
accessed_as_z_ = false;
}
bool AccessedAsZSinceLastLog() const { return accessed_as_z_; }
private:
bool accessed_as_z_;
};
// Representation of a SVE predicate register.
class LogicPRegister {
public:
inline LogicPRegister(
SimPRegister& other) // NOLINT(runtime/references)(runtime/explicit)
: register_(other) {}
// Set a conveniently-sized block to 16 bits as the minimum predicate length
// is 16 bits and allow to be increased to multiples of 16 bits.
typedef uint16_t ChunkType;
// Assign a bit into the end positon of the specified lane.
// The bit is zero-extended if necessary.
void SetActive(VectorFormat vform, int lane_index, bool value) {
int psize = LaneSizeInBytesFromFormat(vform);
int bit_index = lane_index * psize;
int byte_index = bit_index / kBitsPerByte;
int bit_offset = bit_index % kBitsPerByte;
uint8_t byte = register_.GetLane<uint8_t>(byte_index);
register_.Insert(byte_index, ZeroExtend(byte, bit_offset, psize, value));
}
bool IsActive(VectorFormat vform, int lane_index) const {
int psize = LaneSizeInBytesFromFormat(vform);
int bit_index = lane_index * psize;
int byte_index = bit_index / kBitsPerByte;
int bit_offset = bit_index % kBitsPerByte;
uint8_t byte = register_.GetLane<uint8_t>(byte_index);
return ExtractBit(byte, bit_offset);
}
// The accessors for bulk processing.
int GetChunkCount() const {
VIXL_ASSERT((register_.GetSizeInBytes() % sizeof(ChunkType)) == 0);
return register_.GetSizeInBytes() / sizeof(ChunkType);
}
ChunkType GetChunk(int lane) const { return GetActiveMask<ChunkType>(lane); }
void SetChunk(int lane, ChunkType new_value) {
SetActiveMask(lane, new_value);
}
void SetAllBits() {
int chunk_size = sizeof(ChunkType) * kBitsPerByte;
ChunkType bits = GetUintMask(chunk_size);
for (int lane = 0;
lane < (static_cast<int>(register_.GetSizeInBits() / chunk_size));
lane++) {
SetChunk(lane, bits);
}
}
template <typename T>
T GetActiveMask(int lane) const {
return register_.GetLane<T>(lane);
}
template <typename T>
void SetActiveMask(int lane, T new_value) {
register_.Insert<T>(lane, new_value);
}
void Clear() { register_.Clear(); }
bool Aliases(const LogicPRegister& other) const {
return ®ister_ == &other.register_;
}
private:
// The bit assignment is zero-extended to fill the size of predicate element.
uint8_t ZeroExtend(uint8_t byte, int index, int psize, bool value) {
VIXL_ASSERT(index >= 0);
VIXL_ASSERT(index + psize <= kBitsPerByte);
int bits = value ? 1 : 0;
switch (psize) {
case 1:
AssignBit(byte, index, bits);
break;
case 2:
AssignBits(byte, index, 0x03, bits);
break;
case 4:
AssignBits(byte, index, 0x0f, bits);
break;
case 8:
AssignBits(byte, index, 0xff, bits);
break;
default:
VIXL_UNREACHABLE();
return 0;
}
return byte;
}
SimPRegister& register_;
};
// Representation of a vector register, with typed getters and setters for lanes
// and additional information to represent lane state.
class LogicVRegister {
public:
inline LogicVRegister(
SimVRegister& other) // NOLINT(runtime/references)(runtime/explicit)
: register_(other) {
for (size_t i = 0; i < ArrayLength(saturated_); i++) {
saturated_[i] = kNotSaturated;
}
for (size_t i = 0; i < ArrayLength(round_); i++) {
round_[i] = 0;
}
}
int64_t Int(VectorFormat vform, int index) const {
if (IsSVEFormat(vform)) register_.NotifyAccessAsZ();
int64_t element;
switch (LaneSizeInBitsFromFormat(vform)) {
case 8:
element = register_.GetLane<int8_t>(index);
break;
case 16:
element = register_.GetLane<int16_t>(index);
break;
case 32:
element = register_.GetLane<int32_t>(index);
break;
case 64:
element = register_.GetLane<int64_t>(index);
break;
default:
VIXL_UNREACHABLE();
return 0;
}
return element;
}
uint64_t Uint(VectorFormat vform, int index) const {
if (IsSVEFormat(vform)) register_.NotifyAccessAsZ();
uint64_t element;
switch (LaneSizeInBitsFromFormat(vform)) {
case 8:
element = register_.GetLane<uint8_t>(index);
break;
case 16:
element = register_.GetLane<uint16_t>(index);
break;
case 32:
element = register_.GetLane<uint32_t>(index);
break;
case 64:
element = register_.GetLane<uint64_t>(index);
break;
default:
VIXL_UNREACHABLE();
return 0;
}
return element;
}
int UintArray(VectorFormat vform, uint64_t* dst) const {
for (int i = 0; i < LaneCountFromFormat(vform); i++) {
dst[i] = Uint(vform, i);
}
return LaneCountFromFormat(vform);
}
uint64_t UintLeftJustified(VectorFormat vform, int index) const {
return Uint(vform, index) << (64 - LaneSizeInBitsFromFormat(vform));
}
int64_t IntLeftJustified(VectorFormat vform, int index) const {
uint64_t value = UintLeftJustified(vform, index);
int64_t result;
memcpy(&result, &value, sizeof(result));
return result;
}
void SetInt(VectorFormat vform, int index, int64_t value) const {
if (IsSVEFormat(vform)) register_.NotifyAccessAsZ();
switch (LaneSizeInBitsFromFormat(vform)) {
case 8:
register_.Insert(index, static_cast<int8_t>(value));
break;
case 16:
register_.Insert(index, static_cast<int16_t>(value));
break;
case 32:
register_.Insert(index, static_cast<int32_t>(value));
break;
case 64:
register_.Insert(index, static_cast<int64_t>(value));
break;
default:
VIXL_UNREACHABLE();
return;
}
}
void SetIntArray(VectorFormat vform, const int64_t* src) const {
ClearForWrite(vform);
for (int i = 0; i < LaneCountFromFormat(vform); i++) {
SetInt(vform, i, src[i]);
}
}
void SetUint(VectorFormat vform, int index, uint64_t value) const {
if (IsSVEFormat(vform)) register_.NotifyAccessAsZ();
switch (LaneSizeInBitsFromFormat(vform)) {
case 8:
register_.Insert(index, static_cast<uint8_t>(value));
break;
case 16:
register_.Insert(index, static_cast<uint16_t>(value));
break;
case 32:
register_.Insert(index, static_cast<uint32_t>(value));
break;
case 64:
register_.Insert(index, static_cast<uint64_t>(value));
break;
default:
VIXL_UNREACHABLE();
return;
}
}
void SetUintArray(VectorFormat vform, const uint64_t* src) const {
ClearForWrite(vform);
for (int i = 0; i < LaneCountFromFormat(vform); i++) {
SetUint(vform, i, src[i]);
}
}
template <typename T>
T Float(int index) const {
return register_.GetLane<T>(index);
}
template <typename T>
void SetFloat(int index, T value) const {
register_.Insert(index, value);
}
template <typename T>
void SetFloat(VectorFormat vform, int index, T value) const {
if (IsSVEFormat(vform)) register_.NotifyAccessAsZ();
register_.Insert(index, value);
}
void Clear() { register_.Clear(); }
// When setting a result in a register larger than the result itself, the top
// bits of the register must be cleared.
void ClearForWrite(VectorFormat vform) const {
// SVE destinations write whole registers, so we have nothing to clear.
if (IsSVEFormat(vform)) return;
unsigned size = RegisterSizeInBytesFromFormat(vform);
for (unsigned i = size; i < register_.GetSizeInBytes(); i++) {
SetUint(kFormat16B, i, 0);
}
}
// Saturation state for each lane of a vector.
enum Saturation {
kNotSaturated = 0,
kSignedSatPositive = 1 << 0,
kSignedSatNegative = 1 << 1,
kSignedSatMask = kSignedSatPositive | kSignedSatNegative,
kSignedSatUndefined = kSignedSatMask,
kUnsignedSatPositive = 1 << 2,
kUnsignedSatNegative = 1 << 3,
kUnsignedSatMask = kUnsignedSatPositive | kUnsignedSatNegative,
kUnsignedSatUndefined = kUnsignedSatMask
};
// Getters for saturation state.
Saturation GetSignedSaturation(int index) {
return static_cast<Saturation>(saturated_[index] & kSignedSatMask);
}
Saturation GetUnsignedSaturation(int index) {
return static_cast<Saturation>(saturated_[index] & kUnsignedSatMask);
}
// Setters for saturation state.
void ClearSat(int index) { saturated_[index] = kNotSaturated; }
void SetSignedSat(int index, bool positive) {
SetSatFlag(index, positive ? kSignedSatPositive : kSignedSatNegative);
}
void SetUnsignedSat(int index, bool positive) {
SetSatFlag(index, positive ? kUnsignedSatPositive : kUnsignedSatNegative);
}
void SetSatFlag(int index, Saturation sat) {
saturated_[index] = static_cast<Saturation>(saturated_[index] | sat);
VIXL_ASSERT((sat & kUnsignedSatMask) != kUnsignedSatUndefined);
VIXL_ASSERT((sat & kSignedSatMask) != kSignedSatUndefined);
}
// Saturate lanes of a vector based on saturation state.
LogicVRegister& SignedSaturate(VectorFormat vform) {
for (int i = 0; i < LaneCountFromFormat(vform); i++) {
Saturation sat = GetSignedSaturation(i);
if (sat == kSignedSatPositive) {
SetInt(vform, i, MaxIntFromFormat(vform));
} else if (sat == kSignedSatNegative) {
SetInt(vform, i, MinIntFromFormat(vform));
}
}
return *this;
}
LogicVRegister& UnsignedSaturate(VectorFormat vform) {
for (int i = 0; i < LaneCountFromFormat(vform); i++) {
Saturation sat = GetUnsignedSaturation(i);
if (sat == kUnsignedSatPositive) {
SetUint(vform, i, MaxUintFromFormat(vform));
} else if (sat == kUnsignedSatNegative) {
SetUint(vform, i, 0);
}
}
return *this;
}
// Getter for rounding state.
bool GetRounding(int index) { return round_[index]; }
// Setter for rounding state.
void SetRounding(int index, bool round) { round_[index] = round; }
// Round lanes of a vector based on rounding state.
LogicVRegister& Round(VectorFormat vform) {
for (int i = 0; i < LaneCountFromFormat(vform); i++) {
SetUint(vform, i, Uint(vform, i) + (GetRounding(i) ? 1 : 0));
}
return *this;
}
// Unsigned halve lanes of a vector, and use the saturation state to set the
// top bit.
LogicVRegister& Uhalve(VectorFormat vform) {
for (int i = 0; i < LaneCountFromFormat(vform); i++) {
uint64_t val = Uint(vform, i);
SetRounding(i, (val & 1) == 1);
val >>= 1;
if (GetUnsignedSaturation(i) != kNotSaturated) {
// If the operation causes unsigned saturation, the bit shifted into the
// most significant bit must be set.
val |= (MaxUintFromFormat(vform) >> 1) + 1;
}
SetInt(vform, i, val);
}
return *this;
}
// Signed halve lanes of a vector, and use the carry state to set the top bit.
LogicVRegister& Halve(VectorFormat vform) {
for (int i = 0; i < LaneCountFromFormat(vform); i++) {
int64_t val = Int(vform, i);
SetRounding(i, (val & 1) == 1);
val = ExtractSignedBitfield64(63, 1, val); // >>= 1
if (GetSignedSaturation(i) == kNotSaturated) {
SetInt(vform, i, val);
} else {
// If the operation causes signed saturation, the sign bit must be
// inverted.
uint64_t uval = static_cast<uint64_t>(val);
SetUint(vform, i, uval ^ ((MaxUintFromFormat(vform) >> 1) + 1));
}
}
return *this;
}
int LaneCountFromFormat(VectorFormat vform) const {
if (IsSVEFormat(vform)) {
return register_.GetSizeInBits() / LaneSizeInBitsFromFormat(vform);
} else {
return vixl::aarch64::LaneCountFromFormat(vform);
}
}
private:
SimVRegister& register_;
// Allocate one saturation state entry per lane; largest register is type Q,
// and lanes can be a minimum of one byte wide.
Saturation saturated_[kZRegMaxSizeInBytes];
// Allocate one rounding state entry per lane.
bool round_[kZRegMaxSizeInBytes];
};
// Represent an SVE addressing mode and abstract per-lane address generation to
// make iteration easy.
//
// Contiguous accesses are described with a simple base address, the memory
// occupied by each lane (`SetMsizeInBytesLog2()`) and the number of elements in
// each struct (`SetRegCount()`).
//
// Scatter-gather accesses also require a SimVRegister and information about how
// to extract lanes from it.
class LogicSVEAddressVector {
public:
// scalar-plus-scalar
// scalar-plus-immediate
explicit LogicSVEAddressVector(uint64_t base)
: base_(base),
msize_in_bytes_log2_(kUnknownMsizeInBytesLog2),
reg_count_(1),
vector_(NULL),
vector_form_(kFormatUndefined),
vector_mod_(NO_SVE_OFFSET_MODIFIER),
vector_shift_(0) {}
// scalar-plus-vector
// vector-plus-immediate
// `base` should be the constant used for each element. That is, the value
// of `xn`, or `#<imm>`.
// `vector` should be the SimVRegister with offsets for each element. The
// vector format must be specified; SVE scatter/gather accesses typically
// support both 32-bit and 64-bit addressing.
//
// `mod` and `shift` correspond to the modifiers applied to each element in