diff --git a/patch/0120-DTS-files-for-platform-ET6448M-and-IPD6448M.patch b/patch/0120-DTS-files-for-platform-ET6448M-and-IPD6448M.patch
new file mode 100644
index 000000000..9722518b1
--- /dev/null
+++ b/patch/0120-DTS-files-for-platform-ET6448M-and-IPD6448M.patch
@@ -0,0 +1,1644 @@
+From b2fbd02d3e8fbaa354f8a0401863b1d64e48cd5f Mon Sep 17 00:00:00 2001
+From: arheneus <arheneus@marvell.com>
+Date: Thu, 3 Sep 2020 07:56:25 +0530
+Subject: [PATCH] [DTS] DTS files for platform ET6448M and IPD6448M
+
+Signed-off-by: arheneus <arheneus@marvell.com>
+---
+ arch/arm/boot/dts/armada-385-et6448m.dts  | 793 ++++++++++++++++++++++++++++
+ arch/arm/boot/dts/armada-385-ipd6448m.dts | 823 ++++++++++++++++++++++++++++++
+ 2 files changed, 1616 insertions(+)
+ create mode 100644 arch/arm/boot/dts/armada-385-et6448m.dts
+ create mode 100644 arch/arm/boot/dts/armada-385-ipd6448m.dts
+
+diff --git a/arch/arm/boot/dts/armada-385-et6448m.dts b/arch/arm/boot/dts/armada-385-et6448m.dts
+new file mode 100644
+index 0000000..146b8ee
+--- /dev/null
++++ b/arch/arm/boot/dts/armada-385-et6448m.dts
+@@ -0,0 +1,793 @@
++/dts-v1/;
++
++/ {
++	#address-cells = <0x1>;
++	#size-cells = <0x1>;
++	model = "Microsoft-ET6448M-A38X-CUST1";
++	compatible = "marvell,armada-385-ET6448M", "marvell,a385-amc", "marvell,armada385", "marvell,armada380";
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	aliases {
++		gpio0 = "/soc/internal-regs/gpio@18100";
++		gpio1 = "/soc/internal-regs/gpio@18140";
++		serial0 = "/soc/internal-regs/serial@12000";
++		serial1 = "/soc/internal-regs/serial@12100";
++	};
++
++	memory {
++		device_type = "memory";
++		reg = <0x0 0x80000000>;
++	};
++
++	pmu {
++		compatible = "arm,cortex-a9-pmu";
++		interrupts-extended = <0x1 0x3>;
++	};
++
++	soc {
++		compatible = "marvell,armada380-mbus", "simple-bus";
++		#address-cells = <0x2>;
++		#size-cells = <0x1>;
++		controller = <0x2>;
++		interrupt-parent = <0x3>;
++		pcie-mem-aperture = <0xa0000000 0x40000000>;
++		pcie-io-aperture = <0xffe00000 0x100000>;
++		ranges = <0xf0010000 0x0 0xf1000000 0x100000 0x11d0000 0x0 0xfff00000 0x100000>;
++
++		bootrom {
++			compatible = "marvell,bootrom";
++			reg = <0x11d0000 0x0 0x200000>;
++		};
++
++		devbus-bootcs {
++			compatible = "marvell,mvebu-devbus";
++			reg = <0xf0010000 0x10400 0x8>;
++			ranges = <0x0 0x12f0000 0x0 0xffffffff>;
++			#address-cells = <0x1>;
++			#size-cells = <0x1>;
++			clocks = <0x4 0x0>;
++			status = "disabled";
++		};
++
++		devbus-cs0 {
++			compatible = "marvell,mvebu-devbus";
++			reg = <0xf0010000 0x10408 0x8>;
++			ranges = <0x0 0x13e0000 0x0 0xffffffff>;
++			#address-cells = <0x1>;
++			#size-cells = <0x1>;
++			clocks = <0x4 0x0>;
++			status = "disabled";
++		};
++
++		devbus-cs1 {
++			compatible = "marvell,mvebu-devbus";
++			reg = <0xf0010000 0x10410 0x8>;
++			ranges = <0x0 0x13d0000 0x0 0xffffffff>;
++			#address-cells = <0x1>;
++			#size-cells = <0x1>;
++			clocks = <0x4 0x0>;
++			status = "disabled";
++		};
++
++		devbus-cs2 {
++			compatible = "marvell,mvebu-devbus";
++			reg = <0xf0010000 0x10418 0x8>;
++			ranges = <0x0 0x13b0000 0x0 0xffffffff>;
++			#address-cells = <0x1>;
++			#size-cells = <0x1>;
++			clocks = <0x4 0x0>;
++			status = "disabled";
++		};
++
++		devbus-cs3 {
++			compatible = "marvell,mvebu-devbus";
++			reg = <0xf0010000 0x10420 0x8>;
++			ranges = <0x0 0x1370000 0x0 0xffffffff>;
++			#address-cells = <0x1>;
++			#size-cells = <0x1>;
++			clocks = <0x4 0x0>;
++			status = "disabled";
++		};
++
++		internal-regs {
++			compatible = "simple-bus";
++			#address-cells = <0x1>;
++			#size-cells = <0x1>;
++			ranges = <0x0 0xf0010000 0x0 0x100000>;
++
++			sdramc@1400 {
++				compatible = "marvell,armada-xp-sdram-controller";
++				reg = <0x1400 0x500>;
++			};
++
++			cache-controller@8000 {
++				compatible = "arm,pl310-cache";
++				reg = <0x8000 0x1000>;
++				cache-unified;
++				cache-level = <0x2>;
++				arm,double-linefill-incr = <0x1>;
++				arm,double-linefill-wrap = <0x0>;
++				arm,double-linefill = <0x1>;
++				prefetch-data = <0x1>;
++			};
++
++			scu@c000 {
++				compatible = "arm,cortex-a9-scu";
++				reg = <0xc000 0x58>;
++			};
++
++			timer@c600 {
++				compatible = "arm,cortex-a9-twd-timer";
++				reg = <0xc600 0x20>;
++				interrupts = <0x1 0xd 0x301>;
++				clocks = <0x4 0x2>;
++			};
++
++			interrupt-controller@d000 {
++				compatible = "arm,cortex-a9-gic";
++				#interrupt-cells = <0x3>;
++				#size-cells = <0x0>;
++				interrupt-controller;
++				reg = <0xd000 0x1000 0xc100 0x100>;
++				linux,phandle = <0x3>;
++				phandle = <0x3>;
++			};
++
++			spi@10600 {
++				compatible = "marvell,armada-380-spi", "marvell,orion-spi";
++				reg = <0x10600 0x50>;
++				#address-cells = <0x1>;
++				#size-cells = <0x0>;
++				cell-index = <0x0>;
++				interrupts = <0x0 0x1 0x4>;
++				clocks = <0x4 0x0>;
++				status = "disabled";
++			};
++
++			spi@10680 {
++				compatible = "marvell,armada-380-spi", "marvell,orion-spi";
++				reg = <0x10680 0x50>;
++				#address-cells = <0x1>;
++				#size-cells = <0x0>;
++				cell-index = <0x1>;
++				interrupts = <0x0 0x3f 0x4>;
++				clocks = <0x4 0x0>;
++				status = "disabled";
++			};
++
++                        i2c0:i2c@11000 {
++				compatible = "marvell,mv64xxx-i2c";
++				reg = <0x11000 0x20>;
++				#address-cells = <0x1>;
++				#size-cells = <0x0>;
++				interrupts = <0x0 0x2 0x4>;
++				timeout-ms = <0x3e8>;
++				clocks = <0x4 0x0>;
++				status = "okay";
++				clock-frequency = <100000>;
++
++				adt7473@2e {
++					compatible = "national,adt7473";
++					reg = <0x2e>;
++				};
++
++				lm75a@4a {
++					compatible = "national,lm75a";
++					reg = <0x4a>;
++				};
++
++				lm75a@4b {
++					compatible = "national,lm75a";
++					reg = <0x4b>;
++				};
++			};
++
++                        i2c1:i2c@11100 {
++				compatible = "marvell,mv64xxx-i2c";
++				reg = <0x11100 0x20>;
++				#address-cells = <0x1>;
++				#size-cells = <0x0>;
++				interrupts = <0x0 0x3 0x4>;
++				timeout-ms = <0x3e8>;
++				clocks = <0x4 0x0>;
++				status = "okay";
++				clock-frequency = <0x186a0>;
++			};
++
++			serial@12000 {
++				compatible = "snps,dw-apb-uart";
++				reg = <0x12000 0x100>;
++				reg-shift = <0x2>;
++				interrupts = <0x0 0xc 0x4>;
++				reg-io-width = <0x1>;
++				clocks = <0x4 0x0>;
++				status = "okay";
++				pinctrl-names = "default";
++				pinctrl-0 = <0x5>;
++			};
++
++			serial@12100 {
++				compatible = "snps,dw-apb-uart";
++				reg = <0x12100 0x100>;
++				reg-shift = <0x2>;
++				interrupts = <0x0 0xd 0x4>;
++				reg-io-width = <0x1>;
++				clocks = <0x4 0x0>;
++				status = "disabled";
++			};
++
++			pinctrl@18000 {
++				reg = <0x18000 0x20>;
++				compatible = "marvell,mv88f6828-pinctrl";
++
++				ge-rgmii-pins-0 {
++					marvell,pins = "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp11", "mpp12", "mpp13", "mpp14", "mpp15", "mpp16", "mpp17";
++					marvell,function = "ge0";
++					linux,phandle = <0x8>;
++					phandle = <0x8>;
++				};
++
++				ge-rgmii-pins-1 {
++					marvell,pins = "mpp21", "mpp27", "mpp28", "mpp29", "mpp30", "mpp31", "mpp32", "mpp37", "mpp38", "mpp39", "mpp40", "mpp41";
++					marvell,function = "ge1";
++				};
++
++				i2c-pins-0 {
++					marvell,pins = "mpp2", "mpp3";
++					marvell,function = "i2c0";
++				};
++
++				mdio-pins {
++					marvell,pins = "mpp4", "mpp5";
++					marvell,function = "ge";
++					linux,phandle = <0xb>;
++					phandle = <0xb>;
++				};
++
++				ref-clk-pins-0 {
++					marvell,pins = "mpp45";
++					marvell,function = "ref";
++					linux,phandle = <0x9>;
++					phandle = <0x9>;
++				};
++
++				ref-clk-pins-1 {
++					marvell,pins = "mpp46";
++					marvell,function = "ref";
++				};
++
++				spi-pins-0 {
++					marvell,pins = "mpp22", "mpp23", "mpp24", "mpp25";
++					marvell,function = "spi0";
++				};
++
++				spi-pins-1 {
++					marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
++					marvell,function = "spi1";
++				};
++
++				uart-pins-0 {
++					marvell,pins = "mpp0", "mpp1";
++					marvell,function = "ua0";
++					linux,phandle = <0x5>;
++					phandle = <0x5>;
++				};
++
++				uart-pins-1 {
++					marvell,pins = "mpp19", "mpp20";
++					marvell,function = "ua1";
++				};
++
++				sdhci-pins {
++					marvell,pins = "mpp48", "mpp49", "mpp50", "mpp52", "mpp53", "mpp54", "mpp55", "mpp57", "mpp58", "mpp59";
++					marvell,function = "sd0";
++				};
++
++				sata-pins-0 {
++					marvell,pins = "mpp20";
++					marvell,function = "sata0";
++				};
++
++				sata-pins-1 {
++					marvell,pins = "mpp19";
++					marvell,function = "sata1";
++				};
++
++				sata-pins-2 {
++					marvell,pins = "mpp47";
++					marvell,function = "sata2";
++				};
++
++				sata-pins-3 {
++					marvell,pins = "mpp44";
++					marvell,function = "sata3";
++				};
++
++				i2s_pins {
++					marvell,pins = "mpp48", "mpp49", "mpp50", "mpp51", "mpp52", "mpp53";
++					marvell,function = "audio";
++				};
++			};
++
++                        gpio0:gpio@18100 {
++				compatible = "marvell,orion-gpio";
++				reg = <0x18100 0x40>;
++				ngpios = <0x20>;
++				gpio-controller;
++				#gpio-cells = <0x2>;
++				interrupt-controller;
++				#interrupt-cells = <0x2>;
++				interrupts = <0x0 0x35 0x4 0x0 0x36 0x4 0x0 0x37 0x4 0x0 0x38 0x4>;
++			};
++
++                        gpio1:gpio@18140 {
++				compatible = "marvell,orion-gpio";
++				reg = <0x18140 0x40>;
++				ngpios = <0x1c>;
++				gpio-controller;
++				#gpio-cells = <0x2>;
++				interrupt-controller;
++				#interrupt-cells = <0x2>;
++				interrupts = <0x0 0x3a 0x4 0x0 0x3b 0x4 0x0 0x3c 0x4 0x0 0x3d 0x4>;
++			};
++
++			system-controller@18200 {
++				compatible = "marvell,armada-380-system-controller", "marvell,armada-370-xp-system-controller";
++				reg = <0x18200 0x100>;
++			};
++
++			clock-gating-control@18220 {
++				compatible = "marvell,armada-380-gating-clock";
++				reg = <0x18220 0x4>;
++				clocks = <0x4 0x0>;
++				#clock-cells = <0x1>;
++				linux,phandle = <0x7>;
++				phandle = <0x7>;
++			};
++
++			mvebu-sar@18600 {
++				compatible = "marvell,armada-380-core-clock";
++				reg = <0x18600 0x4>;
++				#clock-cells = <0x1>;
++				linux,phandle = <0x4>;
++				phandle = <0x4>;
++			};
++
++			clock-complex@18700 {
++				compatible = "marvell,armada-380-cpu-clock", "marvell,armada-xp-cpu-clock";
++				reg = <0x18700 0xa0 0x1c054 0x40 0xe4260 0x8>;
++				clocks = <0x4 0x1>;
++				#clock-cells = <0x1>;
++				linux,phandle = <0x10>;
++				phandle = <0x10>;
++			};
++
++			mbus-controller@20000 {
++				compatible = "marvell,mbus-controller";
++				reg = <0x20000 0x100 0x20180 0x20 0x20250 0x8 0x20420 0xc>;
++				linux,phandle = <0x2>;
++				phandle = <0x2>;
++			};
++
++			interrupt-controller@20a00 {
++				compatible = "marvell,mpic";
++				reg = <0x20a00 0x2d0 0x21070 0x58>;
++				#interrupt-cells = <0x1>;
++				#size-cells = <0x1>;
++				interrupt-controller;
++				msi-controller;
++				interrupts = <0x1 0xf 0x4>;
++				linux,phandle = <0x1>;
++				phandle = <0x1>;
++			};
++
++			timer@20300 {
++				compatible = "marvell,armada-380-timer", "marvell,armada-xp-timer";
++				reg = <0x20300 0x30 0x21040 0x30>;
++				interrupts-extended = <0x3 0x0 0x8 0x4 0x3 0x0 0x9 0x4 0x3 0x0 0xa 0x4 0x3 0x0 0xb 0x4 0x1 0x5 0x1 0x6>;
++				clocks = <0x4 0x2 0x6>;
++				clock-names = "nbclk", "fixed";
++			};
++
++			watchdog@20300 {
++				compatible = "marvell,armada-380-wdt";
++				reg = <0x20300 0x34 0x20704 0x4 0x18260 0x4>;
++				clocks = <0x4 0x2 0x6>;
++				clock-names = "nbclk", "fixed";
++			};
++
++			cpurst@20800 {
++				compatible = "marvell,armada-370-cpu-reset";
++				reg = <0x20800 0x10>;
++			};
++
++			mpcore-soc-ctrl@20d20 {
++				compatible = "marvell,armada-380-mpcore-soc-ctrl";
++				reg = <0x20d20 0x6c>;
++			};
++
++			coherency-fabric@21010 {
++				compatible = "marvell,armada-380-coherency-fabric";
++				reg = <0x21010 0x1c>;
++			};
++
++			pmsu@22000 {
++				compatible = "marvell,armada-380-pmsu";
++				reg = <0x22000 0x1000 0x20280 0x4>;
++			};
++
++			ethernet@70000 {
++				compatible = "marvell,armada-370-neta";
++				reg = <0x70000 0x4000>;
++				interrupts-extended = <0x1 0x8>;
++				clocks = <0x7 0x4>;
++				tx-csum-limit = <0x2648>;
++				status = "disabled";
++				pinctrl-names = "default";
++				pinctrl-0 = <0x8 0x9>;
++				phy = <0xa>;
++				phy-mode = "rgmii-id";
++			};
++
++			ethernet@30000 {
++				compatible = "marvell,armada-370-neta";
++				reg = <0x30000 0x4000>;
++				interrupts-extended = <0x1 0xa>;
++				clocks = <0x7 0x3>;
++				status = "disabled";
++			};
++
++			ethernet@34000 {
++				compatible = "marvell,armada-370-neta";
++				reg = <0x34000 0x4000>;
++				interrupts-extended = <0x1 0xc>;
++				clocks = <0x7 0x2>;
++				status = "disabled";
++			};
++
++			usb@58000 {
++				compatible = "marvell,orion-ehci";
++				reg = <0x58000 0x500>;
++				interrupts = <0x0 0x12 0x4>;
++				clocks = <0x7 0x12>;
++				status = "okay";
++			};
++
++			xor@60800 {
++				compatible = "marvell,armada-380-xor", "marvell,orion-xor";
++				reg = <0x60800 0x100 0x60a00 0x100>;
++				clocks = <0x7 0x16>;
++				status = "okay";
++
++				xor00 {
++					interrupts = <0x0 0x16 0x4>;
++					dmacap,memcpy;
++					dmacap,xor;
++				};
++
++				xor01 {
++					interrupts = <0x0 0x17 0x4>;
++					dmacap,memcpy;
++					dmacap,xor;
++					dmacap,memset;
++				};
++			};
++
++			xor@60900 {
++				compatible = "marvell,armada-380-xor", "marvell,orion-xor";
++				reg = <0x60900 0x100 0x60b00 0x100>;
++				clocks = <0x7 0x1c>;
++				status = "okay";
++
++				xor10 {
++					interrupts = <0x0 0x41 0x4>;
++					dmacap,memcpy;
++					dmacap,xor;
++				};
++
++				xor11 {
++					interrupts = <0x0 0x42 0x4>;
++					dmacap,memcpy;
++					dmacap,xor;
++					dmacap,memset;
++				};
++			};
++
++			mdio@72004 {
++				#address-cells = <0x1>;
++				#size-cells = <0x0>;
++				compatible = "marvell,orion-mdio";
++				reg = <0x72004 0x4>;
++				clocks = <0x7 0x4>;
++				pinctrl-names = "default";
++				pinctrl-0 = <0xb>;
++
++				ethernet-phy@1 {
++					reg = <0x1>;
++					linux,phandle = <0xa>;
++					phandle = <0xa>;
++				};
++			};
++
++			crypto@90000 {
++				compatible = "marvell,armada-38x-crypto";
++				reg = <0x90000 0x10000>;
++				reg-names = "regs";
++				interrupts = <0x0 0x13 0x4 0x0 0x14 0x4>;
++				clocks = <0x7 0x17 0x7 0x15 0x7 0xe 0x7 0x10>;
++				clock-names = "cesa0", "cesa1", "cesaz0", "cesaz1";
++				marvell,crypto-srams = <0xc 0xd>;
++				marvell,crypto-sram-size = <0x800>;
++			};
++
++			sata@a8000 {
++				compatible = "marvell,armada-380-ahci";
++				reg = <0xa8000 0x2000>;
++				interrupts = <0x0 0x1a 0x4>;
++				clocks = <0x7 0xf>;
++				status = "disabled";
++			};
++
++			sata@e0000 {
++				compatible = "marvell,armada-380-ahci";
++				reg = <0xe0000 0x2000>;
++				interrupts = <0x0 0x1c 0x4>;
++				clocks = <0x7 0x1e>;
++				status = "disabled";
++			};
++
++			clock@e4250 {
++				compatible = "marvell,armada-380-corediv-clock";
++				reg = <0xe4250 0xc>;
++				#clock-cells = <0x1>;
++				clocks = <0xe>;
++				clock-output-names = "nand";
++				linux,phandle = <0xf>;
++				phandle = <0xf>;
++			};
++
++			thermal@e8078 {
++				compatible = "marvell,armada380-thermal";
++				reg = <0xe4078 0x4 0xe4070 0x8 0xe4100 0x20>;
++				interrupts = <0x0 0x4e 0x4>;
++				threshold = <0x64>;
++				hysteresis = <0x2>;
++				status = "okay";
++			};
++
++			flash@d0000 {
++				compatible = "marvell,armada370-nand";
++				reg = <0xd0000 0x54>;
++				#address-cells = <0x1>;
++				#size-cells = <0x1>;
++				interrupts = <0x0 0x54 0x4>;
++				clocks = <0xf 0x0>;
++				status = "okay";
++				num-cs = <0x1>;
++				marvell,nand-keep-config;
++				marvell,nand-enable-arbiter;
++				nand-on-flash-bbt;
++				partition@0 {
++					label = "U-Boot";
++					reg = <0x0 0xa00000>;
++				};
++
++				partition@A00000 {
++					label = "ONIE";
++					reg = <0xa00000 0x1400000>;
++				};
++
++				partition@1E00000 {
++					/* sonic - 4066MB */
++					label = "SONIC";
++					reg = <0x1e00000 0xfe200000>;
++				};
++			};
++
++			sdhci@d8000 {
++				compatible = "marvell,armada-380-sdhci";
++				reg-names = "sdhci", "mbus", "conf-sdio3";
++				reg = <0xd8000 0x1000 0xdc000 0x100 0x18454 0x4>;
++				interrupts = <0x0 0x19 0x4>;
++				clocks = <0x7 0x11>;
++				mrvl,clk-delay-cycles = <0x1f>;
++				status = "disabled";
++			};
++
++			usb3@f0000 {
++				compatible = "marvell,armada-380-xhci";
++				reg = <0xf0000 0x4000 0xf4000 0x4000>;
++				interrupts = <0x0 0x10 0x4>;
++				clocks = <0x7 0x9>;
++				status = "disabled";
++			};
++
++			usb3@f8000 {
++				compatible = "marvell,armada-380-xhci";
++				reg = <0xf8000 0x4000 0xfc000 0x4000>;
++				interrupts = <0x0 0x11 0x4>;
++				clocks = <0x7 0xa>;
++				status = "disabled";
++			};
++		};
++
++		sa-sram0 {
++			compatible = "mmio-sram";
++			reg = <0x9190000 0x0 0x800>;
++			clocks = <0x7 0x17>;
++			#address-cells = <0x1>;
++			#size-cells = <0x1>;
++			ranges = <0x0 0x9190000 0x0 0x800>;
++			linux,phandle = <0xc>;
++			phandle = <0xc>;
++		};
++
++		sa-sram1 {
++			compatible = "mmio-sram";
++			reg = <0x9150000 0x0 0x800>;
++			clocks = <0x7 0x15>;
++			#address-cells = <0x1>;
++			#size-cells = <0x1>;
++			ranges = <0x0 0x9150000 0x0 0x800>;
++			linux,phandle = <0xd>;
++			phandle = <0xd>;
++		};
++
++		pcie-controller {
++			compatible = "marvell,armada-370-pcie";
++			status = "okay";
++			device_type = "pci";
++			#address-cells = <0x3>;
++			#size-cells = <0x2>;
++			msi-parent = <0x1>;
++			bus-range = <0x0 0xff>;
++			ranges = <0x82000000 0x0 0x80000 0xf0010000 0x80000 0x0 0x2000 0x82000000 0x0 0x40000 0xf0010000 0x40000 0x0 0x2000 0x82000000 0x0 0x44000 0xf0010000 0x44000 0x0 0x2000 0x82000000 0x0 0x48000 0xf0010000 0x48000 0x0 0x2000 0x82000000 0x1 0x0 0x8e80000 0x0 0x1 0x0 0x81000000 0x1 0x0 0x8e00000 0x0 0x1 0x0 0x82000000 0x2 0x0 0x4e80000 0x0 0x1 0x0 0x81000000 0x2 0x0 0x4e00000 0x0 0x1 0x0 0x82000000 0x3 0x0 0x4d80000 0x0 0x1 0x0 0x81000000 0x3 0x0 0x4d00000 0x0 0x1 0x0 0x82000000 0x4 0x0 0x4b80000 0x0 0x1 0x0 0x81000000 0x4 0x0 0x4b00000 0x0 0x1 0x0>;
++
++			pcie@1,0 {
++				device_type = "pci";
++				assigned-addresses = <0x82000800 0x0 0x80000 0x0 0x2000>;
++				reg = <0x800 0x0 0x0 0x0 0x0>;
++				#address-cells = <0x3>;
++				#size-cells = <0x2>;
++				#interrupt-cells = <0x1>;
++				ranges = <0x82000000 0x0 0x0 0x82000000 0x1 0x0 0x1 0x0 0x81000000 0x0 0x0 0x81000000 0x1 0x0 0x1 0x0>;
++				interrupt-map-mask = <0x0 0x0 0x0 0x0>;
++				interrupt-map = <0x0 0x0 0x0 0x0 0x3 0x0 0x1d 0x4>;
++				marvell,pcie-port = <0x0>;
++				marvell,pcie-lane = <0x0>;
++				clocks = <0x7 0x8>;
++				status = "okay";
++			};
++
++			pcie@2,0 {
++				device_type = "pci";
++				assigned-addresses = <0x82000800 0x0 0x40000 0x0 0x2000>;
++				reg = <0x1000 0x0 0x0 0x0 0x0>;
++				#address-cells = <0x3>;
++				#size-cells = <0x2>;
++				#interrupt-cells = <0x1>;
++				ranges = <0x82000000 0x0 0x0 0x82000000 0x2 0x0 0x1 0x0 0x81000000 0x0 0x0 0x81000000 0x2 0x0 0x1 0x0>;
++				interrupt-map-mask = <0x0 0x0 0x0 0x0>;
++				interrupt-map = <0x0 0x0 0x0 0x0 0x3 0x0 0x21 0x4>;
++				marvell,pcie-port = <0x1>;
++				marvell,pcie-lane = <0x0>;
++				clocks = <0x7 0x5>;
++				status = "okay";
++			};
++
++			pcie@3,0 {
++				device_type = "pci";
++				assigned-addresses = <0x82000800 0x0 0x44000 0x0 0x2000>;
++				reg = <0x1800 0x0 0x0 0x0 0x0>;
++				#address-cells = <0x3>;
++				#size-cells = <0x2>;
++				#interrupt-cells = <0x1>;
++				ranges = <0x82000000 0x0 0x0 0x82000000 0x3 0x0 0x1 0x0 0x81000000 0x0 0x0 0x81000000 0x3 0x0 0x1 0x0>;
++				interrupt-map-mask = <0x0 0x0 0x0 0x0>;
++				interrupt-map = <0x0 0x0 0x0 0x0 0x3 0x0 0x46 0x4>;
++				marvell,pcie-port = <0x2>;
++				marvell,pcie-lane = <0x0>;
++				clocks = <0x7 0x6>;
++				status = "disabled";
++			};
++
++			pcie@4,0 {
++				device_type = "pci";
++				assigned-addresses = <0x82000800 0x0 0x48000 0x0 0x2000>;
++				reg = <0x2000 0x0 0x0 0x0 0x0>;
++				#address-cells = <0x3>;
++				#size-cells = <0x2>;
++				#interrupt-cells = <0x1>;
++				ranges = <0x82000000 0x0 0x0 0x82000000 0x4 0x0 0x1 0x0 0x81000000 0x0 0x0 0x81000000 0x4 0x0 0x1 0x0>;
++				interrupt-map-mask = <0x0 0x0 0x0 0x0>;
++				interrupt-map = <0x0 0x0 0x0 0x0 0x3 0x0 0x47 0x4>;
++				marvell,pcie-port = <0x3>;
++				marvell,pcie-lane = <0x0>;
++				clocks = <0x7 0x7>;
++				status = "disabled";
++			};
++		};
++			i2cmux {
++				compatible = "i2c-mux-gpio";
++				#address-cells = <1>;
++				#size-cells = <0>;
++				/* mux-gpios = <&gpio1 20 0 &gpio1 18 0>;  //gpio50 and 52, mind this line and check on the real H/W */
++				mux-gpios = <&gpio1 18 0 &gpio1 20 0>;
++				i2c-parent = <&i2c0>;
++
++				i2c@0 {
++					reg = <0>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++				};
++
++				i2c@1 {
++					reg = <1>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++				};
++
++				i2c@2 {
++					reg = <2>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++				};
++
++				i2c@3 {
++					reg = <3>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++				};
++                        };
++
++	};
++
++	clocks {
++
++		mainpll {
++			compatible = "fixed-clock";
++			#clock-cells = <0x0>;
++			clock-frequency = <0x3b9aca00>;
++			linux,phandle = <0xe>;
++			phandle = <0xe>;
++		};
++
++		oscillator {
++			compatible = "fixed-clock";
++			#clock-cells = <0x0>;
++			clock-frequency = <0x17d7840>;
++			linux,phandle = <0x6>;
++			phandle = <0x6>;
++		};
++	};
++
++	cpus {
++		#address-cells = <0x1>;
++		#size-cells = <0x0>;
++		enable-method = "marvell,armada-380-smp";
++
++		cpu@0 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a9";
++			reg = <0x0>;
++			clocks = <0x10 0x0>;
++			clock-latency = <0xf4240>;
++			clock-names = "cpu0";
++		};
++
++		cpu@1 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a9";
++			reg = <0x1>;
++			clocks = <0x10 0x0>;
++			clock-latency = <0xf4240>;
++			clock-names = "cpu1";
++		};
++	};
++};
++
++
++
+diff --git a/arch/arm/boot/dts/armada-385-ipd6448m.dts b/arch/arm/boot/dts/armada-385-ipd6448m.dts
+new file mode 100644
+index 0000000..b749f58
+--- /dev/null
++++ b/arch/arm/boot/dts/armada-385-ipd6448m.dts
+@@ -0,0 +1,823 @@
++/dts-v1/;
++
++/ {
++	#address-cells = <0x1>;
++	#size-cells = <0x1>;
++	model = "Nokia-IPD6448M-A38X-CUST1";
++	compatible = "marvell,armada-385-IPD6448M", "marvell,a385-amc", "marvell,armada385", "marvell,armada380";
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	aliases {
++		gpio0 = "/soc/internal-regs/gpio@18100";
++		gpio1 = "/soc/internal-regs/gpio@18140";
++		serial0 = "/soc/internal-regs/serial@12000";
++		serial1 = "/soc/internal-regs/serial@12100";
++	};
++
++	memory {
++		device_type = "memory";
++		reg = <0x0 0x80000000>;
++	};
++
++	pmu {
++		compatible = "arm,cortex-a9-pmu";
++		interrupts-extended = <0x1 0x3>;
++	};
++
++	soc {
++		compatible = "marvell,armada380-mbus", "simple-bus";
++		#address-cells = <0x2>;
++		#size-cells = <0x1>;
++		controller = <0x2>;
++		interrupt-parent = <0x3>;
++                pcie-mem-aperture = <0xe0000000 0x10000000>;
++		ranges = <0xf0010000 0x0 0xf1000000 0x100000 0x11d0000 0x0 0xfff00000 0x100000>;
++
++		bootrom {
++			compatible = "marvell,bootrom";
++			reg = <0x11d0000 0x0 0x200000>;
++		};
++
++		devbus-bootcs {
++			compatible = "marvell,mvebu-devbus";
++			reg = <0xf0010000 0x10400 0x8>;
++			ranges = <0x0 0x12f0000 0x0 0xffffffff>;
++			#address-cells = <0x1>;
++			#size-cells = <0x1>;
++			clocks = <0x4 0x0>;
++			status = "disabled";
++		};
++
++		devbus-cs0 {
++			compatible = "marvell,mvebu-devbus";
++			reg = <0xf0010000 0x10408 0x8>;
++			ranges = <0x0 0x13e0000 0x0 0xffffffff>;
++			#address-cells = <0x1>;
++			#size-cells = <0x1>;
++			clocks = <0x4 0x0>;
++			status = "disabled";
++		};
++
++		devbus-cs1 {
++			compatible = "marvell,mvebu-devbus";
++			reg = <0xf0010000 0x10410 0x8>;
++			ranges = <0x0 0x13d0000 0x0 0xffffffff>;
++			#address-cells = <0x1>;
++			#size-cells = <0x1>;
++			clocks = <0x4 0x0>;
++			status = "disabled";
++		};
++
++		devbus-cs2 {
++			compatible = "marvell,mvebu-devbus";
++			reg = <0xf0010000 0x10418 0x8>;
++			ranges = <0x0 0x13b0000 0x0 0xffffffff>;
++			#address-cells = <0x1>;
++			#size-cells = <0x1>;
++			clocks = <0x4 0x0>;
++			status = "disabled";
++		};
++
++		devbus-cs3 {
++			compatible = "marvell,mvebu-devbus";
++			reg = <0xf0010000 0x10420 0x8>;
++			ranges = <0x0 0x1370000 0x0 0xffffffff>;
++			#address-cells = <0x1>;
++			#size-cells = <0x1>;
++			clocks = <0x4 0x0>;
++			status = "disabled";
++		};
++
++		internal-regs {
++			compatible = "simple-bus";
++			#address-cells = <0x1>;
++			#size-cells = <0x1>;
++			ranges = <0x0 0xf0010000 0x0 0x100000>;
++
++			sdramc@1400 {
++				compatible = "marvell,armada-xp-sdram-controller";
++				reg = <0x1400 0x500>;
++			};
++
++			cache-controller@8000 {
++				compatible = "arm,pl310-cache";
++				reg = <0x8000 0x1000>;
++				cache-unified;
++				cache-level = <0x2>;
++				arm,double-linefill-incr = <0x1>;
++				arm,double-linefill-wrap = <0x0>;
++				arm,double-linefill = <0x1>;
++				prefetch-data = <0x1>;
++			};
++
++			scu@c000 {
++				compatible = "arm,cortex-a9-scu";
++				reg = <0xc000 0x58>;
++			};
++
++			timer@c600 {
++				compatible = "arm,cortex-a9-twd-timer";
++				reg = <0xc600 0x20>;
++				interrupts = <0x1 0xd 0x301>;
++				clocks = <0x4 0x2>;
++			};
++
++			interrupt-controller@d000 {
++				compatible = "arm,cortex-a9-gic";
++				#interrupt-cells = <0x3>;
++				#size-cells = <0x0>;
++				interrupt-controller;
++				reg = <0xd000 0x1000 0xc100 0x100>;
++				linux,phandle = <0x3>;
++				phandle = <0x3>;
++			};
++
++			spi@10600 {
++				compatible = "marvell,armada-380-spi", "marvell,orion-spi";
++				reg = <0x10600 0x50>;
++				#address-cells = <0x1>;
++				#size-cells = <0x0>;
++				cell-index = <0x0>;
++				interrupts = <0x0 0x1 0x4>;
++				clocks = <0x4 0x0>;
++                                status = "okay";
++
++				spi-flash@0 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++                                        compatible = "w25q128";
++					reg = <0>; /* Chip select 0 */
++					spi-max-frequency = <108000000>;
++					mtd0@00000000 {
++						label = "U-Boot";
++						reg = <0x00000000 0x00200000>;
++						read-only;
++					};
++
++					mtd1@00200000 {
++						label = "uboot-env";
++						reg = <0x00200000 0x01000000>;
++					};
++				};
++
++			};
++
++			spi@10680 {
++				compatible = "marvell,armada-380-spi", "marvell,orion-spi";
++				reg = <0x10680 0x50>;
++				#address-cells = <0x1>;
++				#size-cells = <0x0>;
++				cell-index = <0x1>;
++				interrupts = <0x0 0x3f 0x4>;
++				clocks = <0x4 0x0>;
++				status = "disabled";
++			};
++
++                        i2c0:i2c@11000 {
++				compatible = "marvell,mv64xxx-i2c";
++				reg = <0x11000 0x20>;
++				#address-cells = <0x1>;
++				#size-cells = <0x0>;
++				interrupts = <0x0 0x2 0x4>;
++				timeout-ms = <0x3e8>;
++				clocks = <0x4 0x0>;
++				status = "okay";
++				clock-frequency = <100000>;
++
++				adt7473@2e {
++					compatible = "national,adt7473";
++					reg = <0x2e>;
++				};
++
++				lm75a@4a {
++					compatible = "nxp,pct2075";
++					reg = <0x4a>;
++				};
++
++				lm75a@4b {
++					compatible = "nxp,pct2075";
++					reg = <0x4b>;
++				};
++			};
++
++                        i2c1:i2c@11100 {
++				compatible = "marvell,mv64xxx-i2c";
++				reg = <0x11100 0x20>;
++				#address-cells = <0x1>;
++				#size-cells = <0x0>;
++				interrupts = <0x0 0x3 0x4>;
++				timeout-ms = <0x3e8>;
++				clocks = <0x4 0x0>;
++				status = "okay";
++				clock-frequency = <0x186a0>;
++			};
++
++			serial@12000 {
++				compatible = "snps,dw-apb-uart";
++				reg = <0x12000 0x100>;
++				reg-shift = <0x2>;
++				interrupts = <0x0 0xc 0x4>;
++				reg-io-width = <0x1>;
++				clocks = <0x4 0x0>;
++				status = "okay";
++				pinctrl-names = "default";
++				pinctrl-0 = <0x5>;
++			};
++
++			serial@12100 {
++				compatible = "snps,dw-apb-uart";
++				reg = <0x12100 0x100>;
++				reg-shift = <0x2>;
++				interrupts = <0x0 0xd 0x4>;
++				reg-io-width = <0x1>;
++				clocks = <0x4 0x0>;
++				status = "disabled";
++			};
++
++			pinctrl@18000 {
++				reg = <0x18000 0x20>;
++				compatible = "marvell,mv88f6828-pinctrl";
++
++				ge-rgmii-pins-0 {
++					marvell,pins = "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp11", "mpp12", "mpp13", "mpp14", "mpp15", "mpp16", "mpp17";
++					marvell,function = "ge0";
++					linux,phandle = <0x8>;
++					phandle = <0x8>;
++				};
++
++				ge-rgmii-pins-1 {
++					marvell,pins = "mpp21", "mpp27", "mpp28", "mpp29", "mpp30", "mpp31", "mpp32", "mpp37", "mpp38", "mpp39", "mpp40", "mpp41";
++					marvell,function = "ge1";
++				};
++
++				i2c-pins-0 {
++					marvell,pins = "mpp2", "mpp3";
++					marvell,function = "i2c0";
++				};
++
++				mdio-pins {
++					marvell,pins = "mpp4", "mpp5";
++					marvell,function = "ge";
++					linux,phandle = <0xb>;
++					phandle = <0xb>;
++				};
++
++				ref-clk-pins-0 {
++					marvell,pins = "mpp45";
++					marvell,function = "ref";
++					linux,phandle = <0x9>;
++					phandle = <0x9>;
++				};
++
++				ref-clk-pins-1 {
++					marvell,pins = "mpp46";
++					marvell,function = "ref";
++				};
++
++				spi-pins-0 {
++					marvell,pins = "mpp22", "mpp23", "mpp24", "mpp25";
++					marvell,function = "spi0";
++				};
++
++				spi-pins-1 {
++					marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
++					marvell,function = "spi1";
++				};
++
++				uart-pins-0 {
++					marvell,pins = "mpp0", "mpp1";
++					marvell,function = "ua0";
++					linux,phandle = <0x5>;
++					phandle = <0x5>;
++				};
++
++				uart-pins-1 {
++					marvell,pins = "mpp19", "mpp20";
++					marvell,function = "ua1";
++				};
++
++				sdhci-pins {
++					marvell,pins = "mpp48", "mpp49", "mpp50", "mpp52", "mpp53", "mpp54", "mpp55", "mpp57", "mpp58", "mpp59";
++					marvell,function = "sd0";
++				};
++
++				sata-pins-0 {
++					marvell,pins = "mpp20";
++					marvell,function = "sata0";
++				};
++
++				sata-pins-1 {
++					marvell,pins = "mpp19";
++					marvell,function = "sata1";
++				};
++
++				sata-pins-2 {
++					marvell,pins = "mpp47";
++					marvell,function = "sata2";
++				};
++
++				sata-pins-3 {
++					marvell,pins = "mpp44";
++					marvell,function = "sata3";
++				};
++
++				i2s_pins {
++					marvell,pins = "mpp48", "mpp49", "mpp50", "mpp51", "mpp52", "mpp53";
++					marvell,function = "audio";
++				};
++			};
++
++                        gpio0:gpio@18100 {
++				compatible = "marvell,orion-gpio";
++				reg = <0x18100 0x40>;
++				ngpios = <0x20>;
++				gpio-controller;
++				#gpio-cells = <0x2>;
++				interrupt-controller;
++				#interrupt-cells = <0x2>;
++				interrupts = <0x0 0x35 0x4 0x0 0x36 0x4 0x0 0x37 0x4 0x0 0x38 0x4>;
++			};
++
++                        gpio1:gpio@18140 {
++				compatible = "marvell,orion-gpio";
++				reg = <0x18140 0x40>;
++				ngpios = <0x1c>;
++				gpio-controller;
++				#gpio-cells = <0x2>;
++				interrupt-controller;
++				#interrupt-cells = <0x2>;
++				interrupts = <0x0 0x3a 0x4 0x0 0x3b 0x4 0x0 0x3c 0x4 0x0 0x3d 0x4>;
++			};
++
++			system-controller@18200 {
++				compatible = "marvell,armada-380-system-controller", "marvell,armada-370-xp-system-controller";
++				reg = <0x18200 0x100>;
++			};
++
++			clock-gating-control@18220 {
++				compatible = "marvell,armada-380-gating-clock";
++				reg = <0x18220 0x4>;
++				clocks = <0x4 0x0>;
++				#clock-cells = <0x1>;
++				linux,phandle = <0x7>;
++				phandle = <0x7>;
++			};
++
++			mvebu-sar@18600 {
++				compatible = "marvell,armada-380-core-clock";
++				reg = <0x18600 0x4>;
++				#clock-cells = <0x1>;
++				linux,phandle = <0x4>;
++				phandle = <0x4>;
++			};
++
++			clock-complex@18700 {
++				compatible = "marvell,armada-380-cpu-clock", "marvell,armada-xp-cpu-clock";
++				reg = <0x18700 0xa0 0x1c054 0x40 0xe4260 0x8>;
++				clocks = <0x4 0x1>;
++				#clock-cells = <0x1>;
++				linux,phandle = <0x10>;
++				phandle = <0x10>;
++			};
++
++			mbus-controller@20000 {
++				compatible = "marvell,mbus-controller";
++				reg = <0x20000 0x100 0x20180 0x20 0x20250 0x8 0x20420 0xc>;
++				linux,phandle = <0x2>;
++				phandle = <0x2>;
++			};
++
++			interrupt-controller@20a00 {
++				compatible = "marvell,mpic";
++				reg = <0x20a00 0x2d0 0x21070 0x58>;
++				#interrupt-cells = <0x1>;
++				#size-cells = <0x1>;
++				interrupt-controller;
++				msi-controller;
++				interrupts = <0x1 0xf 0x4>;
++				linux,phandle = <0x1>;
++				phandle = <0x1>;
++			};
++
++			timer@20300 {
++				compatible = "marvell,armada-380-timer", "marvell,armada-xp-timer";
++				reg = <0x20300 0x30 0x21040 0x30>;
++				interrupts-extended = <0x3 0x0 0x8 0x4 0x3 0x0 0x9 0x4 0x3 0x0 0xa 0x4 0x3 0x0 0xb 0x4 0x1 0x5 0x1 0x6>;
++				clocks = <0x4 0x2 0x6>;
++				clock-names = "nbclk", "fixed";
++			};
++
++			watchdog@20300 {
++				compatible = "marvell,armada-380-wdt";
++				reg = <0x20300 0x34 0x20704 0x4 0x18260 0x4>;
++				clocks = <0x4 0x2 0x6>;
++				clock-names = "nbclk", "fixed";
++			};
++
++			cpurst@20800 {
++				compatible = "marvell,armada-370-cpu-reset";
++				reg = <0x20800 0x10>;
++			};
++
++			mpcore-soc-ctrl@20d20 {
++				compatible = "marvell,armada-380-mpcore-soc-ctrl";
++				reg = <0x20d20 0x6c>;
++			};
++
++			coherency-fabric@21010 {
++				compatible = "marvell,armada-380-coherency-fabric";
++				reg = <0x21010 0x1c>;
++			};
++
++			pmsu@22000 {
++				compatible = "marvell,armada-380-pmsu";
++				reg = <0x22000 0x1000 0x20280 0x4>;
++			};
++
++			ethernet@70000 {
++				compatible = "marvell,armada-370-neta";
++				reg = <0x70000 0x4000>;
++				interrupts-extended = <0x1 0x8>;
++				clocks = <0x7 0x4>;
++				tx-csum-limit = <0x2648>;
++				status = "disabled";
++				pinctrl-names = "default";
++				pinctrl-0 = <0x8 0x9>;
++				phy = <0xa>;
++				phy-mode = "rgmii-id";
++			};
++
++			ethernet@30000 {
++				compatible = "marvell,armada-370-neta";
++				reg = <0x30000 0x4000>;
++				interrupts-extended = <0x1 0xa>;
++				clocks = <0x7 0x3>;
++				status = "disabled";
++			};
++
++			ethernet@34000 {
++				compatible = "marvell,armada-370-neta";
++				reg = <0x34000 0x4000>;
++				interrupts-extended = <0x1 0xc>;
++				clocks = <0x7 0x2>;
++				status = "disabled";
++			};
++
++			usb@58000 {
++				compatible = "marvell,orion-ehci";
++				reg = <0x58000 0x500>;
++				interrupts = <0x0 0x12 0x4>;
++				clocks = <0x7 0x12>;
++				status = "okay";
++			};
++
++			xor@60800 {
++				compatible = "marvell,armada-380-xor", "marvell,orion-xor";
++				reg = <0x60800 0x100 0x60a00 0x100>;
++				clocks = <0x7 0x16>;
++				status = "okay";
++
++				xor00 {
++					interrupts = <0x0 0x16 0x4>;
++					dmacap,memcpy;
++					dmacap,xor;
++				};
++
++				xor01 {
++					interrupts = <0x0 0x17 0x4>;
++					dmacap,memcpy;
++					dmacap,xor;
++					dmacap,memset;
++				};
++			};
++
++			xor@60900 {
++				compatible = "marvell,armada-380-xor", "marvell,orion-xor";
++				reg = <0x60900 0x100 0x60b00 0x100>;
++				clocks = <0x7 0x1c>;
++				status = "okay";
++
++				xor10 {
++					interrupts = <0x0 0x41 0x4>;
++					dmacap,memcpy;
++					dmacap,xor;
++				};
++
++				xor11 {
++					interrupts = <0x0 0x42 0x4>;
++					dmacap,memcpy;
++					dmacap,xor;
++					dmacap,memset;
++				};
++			};
++
++			mdio@72004 {
++				#address-cells = <0x1>;
++				#size-cells = <0x0>;
++				compatible = "marvell,orion-mdio";
++				reg = <0x72004 0x4>;
++				clocks = <0x7 0x4>;
++				pinctrl-names = "default";
++				pinctrl-0 = <0xb>;
++
++				ethernet-phy@1 {
++					reg = <0x1>;
++					linux,phandle = <0xa>;
++					phandle = <0xa>;
++				};
++			};
++
++			crypto@90000 {
++				compatible = "marvell,armada-38x-crypto";
++				reg = <0x90000 0x10000>;
++				reg-names = "regs";
++				interrupts = <0x0 0x13 0x4 0x0 0x14 0x4>;
++				clocks = <0x7 0x17 0x7 0x15 0x7 0xe 0x7 0x10>;
++				clock-names = "cesa0", "cesa1", "cesaz0", "cesaz1";
++				marvell,crypto-srams = <0xc 0xd>;
++				marvell,crypto-sram-size = <0x800>;
++			};
++
++			sata@a8000 {
++				compatible = "marvell,armada-380-ahci";
++				reg = <0xa8000 0x2000>;
++				interrupts = <0x0 0x1a 0x4>;
++				clocks = <0x7 0xf>;
++				status = "okay";
++			};
++
++			sata@e0000 {
++				compatible = "marvell,armada-380-ahci";
++				reg = <0xe0000 0x2000>;
++				interrupts = <0x0 0x1c 0x4>;
++				clocks = <0x7 0x1e>;
++				status = "disabled";
++			};
++
++			clock@e4250 {
++				compatible = "marvell,armada-380-corediv-clock";
++				reg = <0xe4250 0xc>;
++				#clock-cells = <0x1>;
++				clocks = <0xe>;
++				clock-output-names = "nand";
++				linux,phandle = <0xf>;
++				phandle = <0xf>;
++			};
++
++			thermal@e8078 {
++				compatible = "marvell,armada380-thermal";
++				reg = <0xe4078 0x4 0xe4070 0x8 0xe4100 0x20>;
++				interrupts = <0x0 0x4e 0x4>;
++				threshold = <0x64>;
++				hysteresis = <0x2>;
++				status = "okay";
++			};
++
++			flash@d0000 {
++				compatible = "marvell,armada370-nand";
++				reg = <0xd0000 0x54>;
++				#address-cells = <0x1>;
++				#size-cells = <0x1>;
++				interrupts = <0x0 0x54 0x4>;
++				clocks = <0xf 0x0>;
++				status = "disabled";
++				num-cs = <0x1>;
++				marvell,nand-keep-config;
++				marvell,nand-enable-arbiter;
++				nand-on-flash-bbt;
++				partition@0 {
++					label = "U-Boot";
++					reg = <0x0 0xa00000>;
++				};
++
++				partition@A00000 {
++					label = "ONIE";
++					reg = <0xa00000 0x1400000>;
++				};
++
++				partition@1E00000 {
++					/* sonic - 4066MB */
++					label = "SONIC";
++					reg = <0x1e00000 0xfe200000>;
++				};
++			};
++
++			sdhci@d8000 {
++				compatible = "marvell,armada-380-sdhci";
++				reg-names = "sdhci", "mbus", "conf-sdio3";
++				reg = <0xd8000 0x1000 0xdc000 0x100 0x18454 0x4>;
++				interrupts = <0x0 0x19 0x4>;
++				clocks = <0x7 0x11>;
++				mrvl,clk-delay-cycles = <0x1f>;
++				status = "disabled";
++			};
++
++			usb3@f0000 {
++				compatible = "marvell,armada-380-xhci";
++				reg = <0xf0000 0x4000 0xf4000 0x4000>;
++				interrupts = <0x0 0x10 0x4>;
++				clocks = <0x7 0x9>;
++				status = "disabled";
++			};
++
++			usb3@f8000 {
++				compatible = "marvell,armada-380-xhci";
++				reg = <0xf8000 0x4000 0xfc000 0x4000>;
++				interrupts = <0x0 0x11 0x4>;
++				clocks = <0x7 0xa>;
++				status = "disabled";
++			};
++		};
++
++		sa-sram0 {
++			compatible = "mmio-sram";
++			reg = <0x9190000 0x0 0x800>;
++			clocks = <0x7 0x17>;
++			#address-cells = <0x1>;
++			#size-cells = <0x1>;
++			ranges = <0x0 0x9190000 0x0 0x800>;
++			linux,phandle = <0xc>;
++			phandle = <0xc>;
++		};
++
++		sa-sram1 {
++			compatible = "mmio-sram";
++			reg = <0x9150000 0x0 0x800>;
++			clocks = <0x7 0x15>;
++			#address-cells = <0x1>;
++			#size-cells = <0x1>;
++			ranges = <0x0 0x9150000 0x0 0x800>;
++			linux,phandle = <0xd>;
++			phandle = <0xd>;
++		};
++
++		pcie-controller {
++			compatible = "marvell,armada-370-pcie";
++			status = "okay";
++			device_type = "pci";
++			#address-cells = <0x3>;
++			#size-cells = <0x2>;
++			msi-parent = <0x1>;
++			bus-range = <0x0 0xff>;
++			ranges = <0x82000000 0x0 0x80000 0xf0010000 0x80000 0x0 0x2000 
++                                  0x82000000 0x0 0x40000 0xf0010000 0x40000 0x0 0x2000
++                                  0x82000000 0x0 0x44000 0xf0010000 0x44000 0x0 0x2000
++                                  0x82000000 0x0 0x48000 0xf0010000 0x48000 0x0 0x2000 
++                                  0x82000000 0x1 0x0 0x8e80000  0x0     0x1 0x0 
++                                  0x81000000 0x1 0x0 0x8e00000 0x0 0x1 0x0 
++                                  0x82000000 0x2 0x0 0x4e80000 0x0 0x1 0x0 
++                                  0x81000000 0x2 0x0 0x4e00000 0x0 0x1 0x0
++                                  0x82000000 0x3 0x0 0x4d80000 0x0 0x1 0x0 
++                                  0x81000000 0x3 0x0 0x4d00000 0x0 0x1 0x0 
++                                  0x82000000 0x4 0x0 0x4b80000 0x0 0x1 0x0 
++                                  0x81000000 0x4 0x0 0x4b00000 0x0 0x1 0x0>;
++
++			pcie@1,0 {
++				device_type = "pci";
++				assigned-addresses = <0x82000800 0x0 0x80000 0x0 0x2000>;
++				reg = <0x800 0x0 0x0 0x0 0x0>;
++				#address-cells = <0x3>;
++				#size-cells = <0x2>;
++				#interrupt-cells = <0x1>;
++				ranges = <0x82000000 0x0 0x0 0x82000000 0x1 0x0 0x1 0x0 0x81000000 0x0 0x0 0x81000000 0x1 0x0 0x1 0x0>;
++				interrupt-map-mask = <0x0 0x0 0x0 0x0>;
++				interrupt-map = <0x0 0x0 0x0 0x0 0x3 0x0 0x1d 0x4>;
++				marvell,pcie-port = <0x0>;
++				marvell,pcie-lane = <0x0>;
++				clocks = <0x7 0x8>;
++				status = "okay";
++			};
++
++			pcie@2,0 {
++				device_type = "pci";
++				assigned-addresses = <0x82000800 0x0 0x40000 0x0 0x2000>;
++				reg = <0x1000 0x0 0x0 0x0 0x0>;
++				#address-cells = <0x3>;
++				#size-cells = <0x2>;
++				#interrupt-cells = <0x1>;
++				ranges = <0x82000000 0x0 0x0 0x82000000 0x2 0x0 0x1 0x0 
++                                          0x81000000 0x0 0x0 0x81000000 0x2 0x0 0x1 0x0>;
++				interrupt-map-mask = <0x0 0x0 0x0 0x0>;
++				interrupt-map = <0x0 0x0 0x0 0x0 0x3 0x0 0x21 0x4>;
++				marvell,pcie-port = <0x1>;
++				marvell,pcie-lane = <0x0>;
++				clocks = <0x7 0x5>;
++				status = "okay";
++			};
++
++			pcie@3,0 {
++				device_type = "pci";
++				assigned-addresses = <0x82000800 0x0 0x44000 0x0 0x2000>;
++				reg = <0x1800 0x0 0x0 0x0 0x0>;
++				#address-cells = <0x3>;
++				#size-cells = <0x2>;
++				#interrupt-cells = <0x1>;
++				ranges = <0x82000000 0x0 0x0 0x82000000 0x3 0x0 0x1 0x0 0x81000000 0x0 0x0 0x81000000 0x3 0x0 0x1 0x0>;
++				interrupt-map-mask = <0x0 0x0 0x0 0x0>;
++				interrupt-map = <0x0 0x0 0x0 0x0 0x3 0x0 0x46 0x4>;
++				marvell,pcie-port = <0x2>;
++				marvell,pcie-lane = <0x0>;
++				clocks = <0x7 0x6>;
++				status = "disabled";
++			};
++
++			pcie@4,0 {
++				device_type = "pci";
++				assigned-addresses = <0x82000800 0x0 0x48000 0x0 0x2000>;
++				reg = <0x2000 0x0 0x0 0x0 0x0>;
++				#address-cells = <0x3>;
++				#size-cells = <0x2>;
++				#interrupt-cells = <0x1>;
++				ranges = <0x82000000 0x0 0x0 0x82000000 0x4 0x0 0x1 0x0 0x81000000 0x0 0x0 0x81000000 0x4 0x0 0x1 0x0>;
++				interrupt-map-mask = <0x0 0x0 0x0 0x0>;
++				interrupt-map = <0x0 0x0 0x0 0x0 0x3 0x0 0x47 0x4>;
++				marvell,pcie-port = <0x3>;
++				marvell,pcie-lane = <0x0>;
++				clocks = <0x7 0x7>;
++				status = "disabled";
++			};
++		};
++			i2cmux {
++				compatible = "i2c-mux-gpio";
++				#address-cells = <1>;
++				#size-cells = <0>;
++				/* mux-gpios = <&gpio1 20 0 &gpio1 18 0>;  //gpio50 and 52, mind this line and check on the real H/W */
++				mux-gpios = <&gpio1 18 0 &gpio1 20 0>;
++				i2c-parent = <&i2c0>;
++
++				i2c@0 {
++					reg = <0>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++				};
++
++				i2c@1 {
++					reg = <1>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++				};
++
++				i2c@2 {
++					reg = <2>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++				};
++
++				i2c@3 {
++					reg = <3>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++				};
++                        };
++
++	};
++
++	clocks {
++
++		mainpll {
++			compatible = "fixed-clock";
++			#clock-cells = <0x0>;
++			clock-frequency = <0x3b9aca00>;
++			linux,phandle = <0xe>;
++			phandle = <0xe>;
++		};
++
++		oscillator {
++			compatible = "fixed-clock";
++			#clock-cells = <0x0>;
++			clock-frequency = <0x17d7840>;
++			linux,phandle = <0x6>;
++			phandle = <0x6>;
++		};
++	};
++
++	cpus {
++		#address-cells = <0x1>;
++		#size-cells = <0x0>;
++		enable-method = "marvell,armada-380-smp";
++
++		cpu@0 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a9";
++			reg = <0x0>;
++			clocks = <0x10 0x0>;
++			clock-latency = <0xf4240>;
++			clock-names = "cpu0";
++		};
++
++		cpu@1 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a9";
++			reg = <0x1>;
++			clocks = <0x10 0x0>;
++			clock-latency = <0xf4240>;
++			clock-names = "cpu1";
++		};
++	};
++};
++
++
++
+-- 
+2.7.4
+
diff --git a/patch/series b/patch/series
index 13740c230..eabe992a7 100755
--- a/patch/series
+++ b/patch/series
@@ -62,4 +62,6 @@ driver-ixgbe-external-phy.patch
 0011-mlxsw-core-thermal-Separate-temperature-trend-read-c.patch
 0012-Add-support-for-new-transceivers-types-QSFP-DD-and-Q.patch
 0013-watchdog-mlx-wdt-support-new-watchdog-type-with-long.patch
+#Marvell patches
+0120-DTS-files-for-platform-ET6448M-and-IPD6448M.patch