Fuxi.scala

import chisel3.{Bundle, Module}
import chisel3.stage.ChiselGeneratorAnnotation
import circt.stage.ChiselStage

import io._
import axi.AxiMaster
import consts.Parameters.{ADDR_WIDTH, DATA_WIDTH}

import core.Core
import bus.CoreBus

class Fuxi extends Module {
  val io = IO(new Bundle {
    // interrupt request
    val irq       = new InterruptIO
    // for trace generating
    val debug     = new DebugIO
    // AXI interfaces
    val inst      = new AxiMaster(ADDR_WIDTH, DATA_WIDTH)
    val data      = new AxiMaster(ADDR_WIDTH, DATA_WIDTH)
    val uncached  = new AxiMaster(ADDR_WIDTH, DATA_WIDTH)
  })

  val core    = Module(new Core)
  val coreBus = Module(new CoreBus)

  core.io.irq   <> io.irq
  core.io.tlb   <> coreBus.io.tlb
  core.io.cache <> coreBus.io.cache
  core.io.rom   <> coreBus.io.rom
  core.io.ram   <> coreBus.io.ram
  core.io.debug <> io.debug

  coreBus.io.inst     <> io.inst
  coreBus.io.data     <> io.data
  coreBus.io.uncached <> io.uncached
}

object Fuxi extends App {
  private val firtoolOptions = Array(
    "--firtool-option", "-disable-all-randomization",
    "--firtool-option", "-strip-debug-info",
    "--firtool-option", "-default-layer-specialization=enable",
    "--firtool-option", "-lowering-options=disallowLocalVariables,disallowPackedArrays," +
      "disallowPackedStructAssignments,disallowDeclAssignments,noAlwaysComb," +
      "mitigateVivadoArrayIndexConstPropBug"
  )

  (new ChiselStage).execute(
    Array("--target", "verilog") ++ firtoolOptions ++ args,
    Seq(ChiselGeneratorAnnotation(() => new Fuxi))
  )
}