-
Notifications
You must be signed in to change notification settings - Fork 8
/
Copy pathCoCo2.qsf
106 lines (96 loc) · 5.46 KB
/
CoCo2.qsf
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
# --------------------------------------------------------------------------
#
# MiSTer project
#
# WARNING WARNING WARNING:
# Do not add files to project in Quartus IDE! It will mess this file!
# Add the files manually to files.qip file.
#
# --------------------------------------------------------------------------
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition"
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
set_global_assignment -name SEED 1
#set_global_assignment -name VERILOG_MACRO "MISTER_FB=1"
#enable it only if 8bit indexed mode is used in core
#set_global_assignment -name VERILOG_MACRO "MISTER_FB_PALETTE=1"
#do not enable DEBUG_NOHDMI in release!
#set_global_assignment -name VERILOG_MACRO "MISTER_DEBUG_NOHDMI=1"
# disable bilinear filtering when downscaling
#set_global_assignment -name VERILOG_MACRO "MISTER_DOWNSCALE_NN=1"
# disable adaptive scanline filtering
#set_global_assignment -name VERILOG_MACRO "MISTER_DISABLE_ADAPTIVE=1"
#use only 1MB per frame for scaler to free ~21MB DDR3 RAM
#set_global_assignment -name VERILOG_MACRO "MISTER_SMALL_VBUF=1"
source sys/sys.tcl
source sys/sys_analog.tcl
source files.qip
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE ints.stp
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Cassette_Write.sv
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dac.sv
set_global_assignment -name VERILOG_FILE rtl/mc6809i.v
set_global_assignment -name VHDL_FILE rtl/CPU09/cpu09l_128a.vhd
set_global_assignment -name VERILOG_FILE rtl/pll.v -library pll
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dragoncoco.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/acia.sv
set_global_assignment -name VERILOG_FILE rtl/ps2.v
set_global_assignment -name VERILOG_FILE rtl/ram.v
set_global_assignment -name VERILOG_FILE rtl/uart_rx.v
set_global_assignment -name VERILOG_FILE rtl/pia6520.v
set_global_assignment -name VERILOG_FILE rtl/cassette.v
set_global_assignment -name VERILOG_FILE rtl/square_gen.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE roms/rom_chrrom.v
set_global_assignment -name VHDL_FILE dpram.vhd
set_global_assignment -name VHDL_FILE rtl/mc6847pace.vhd
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
set_global_assignment -name VHDL_FILE rtl/dpram_1r1w.vhd
set_global_assignment -name VHDL_FILE rtl/mc6883.vhd
set_global_assignment -name VHDL_FILE rtl/ttl_74LS138.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/fdc.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/wd1793.sv
set_global_assignment -name VHDL_FILE rtl/OVO.vhd
set_global_assignment -name QIP_FILE rtl/cassetteoverlay/cassetteoverlay.qip
set_global_assignment -name SYSTEMVERILOG_FILE CoCo2.sv
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_global_assignment -name SIGNALTAP_FILE ints.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top