Skip to content

Visual S-PPU1/2 transistor simulation #442

@paulb-nl

Description

@paulb-nl

There are transistor simulations of both PPU chips:
PPU1
https://www.qmtpro.com/~nes/chipimages/visual5c77/

Nodenames: https://www.qmtpro.com/~nes/chipimages/visual5c77/nodenames.js

PPU2
https://www.qmtpro.com/~nes/chipimages/visual5c78/

Nodenames: https://www.qmtpro.com/~nes/chipimages/visual5c78/nodenames.js

Not everything works correctly but we can find out a lot of the low level behavior of the chips.

Nodes that seems to be wrongly named or broken:

PPU1

  • _last_on_screen_line, _last_on_screen_line_not_fblanking These seem to be first line of VBlank
  • _spr_vpos_adder_sum This adder seems to be _/oam_vpos + _opvct but should be _/oam_vpos + _opvct + 1 aka opvct - oam_vpos
  • _spr_tile_vofs This V offset is inverted
  • Sprite tile fetching always reads OAM sprite 127

Metadata

Metadata

Assignees

No one assigned

    Labels

    No labels
    No labels

    Type

    No type

    Projects

    No projects

    Milestone

    No milestone

    Relationships

    None yet

    Development

    No branches or pull requests

    Issue actions