Ignoring invalid assign in constant false if statement

[corco]

I'm working on an existing codebase that has modules like this:

module test #(
    parameter int DELAY = 1
) (
    input  logic clk,
    input  [7:0]  in_byte,
    output [7:0]  out_byte
);

  logic [DELAY-1:0][7:0] byte_dl;

  always_ff @(clk) begin
    byte_dl[0] <= in_byte;

    if (DELAY > 1) begin
      byte_dl[DELAY-1:1] <= byte_dl[DELAY-2:0];
    end
  end

  assign out_byte = byte_dl[DELAY-1];

endmodule : test

If DELAY is greater than 1, all is fine.

However, if DELAY==1, slang will error this module because the assignation in the if statement is invalid, even though it would never execute as the if statement will always be false.

Is it possible for slang to ignore "always false paths" in if statements, or have a way downgrade the error to a warning? I understand the prefered way is to use a generate block, but this syntax is accepted by synthesis tool and pass the "logically ok" test.

[MikePopoloski]

Yeah, I think both of these are reasonable: the specific error here can be made suppressible, and also we can try harder to detect if statements that have known constant false values. That will always be based on heuristics since slang isn't going to do a full constant propagation pass at this point in AST construction but for simple cases it should be doable.