Module Duplication during Compilation #670
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I'm toying around with |
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Yes, currently one per instance. I previously had a cache to avoid creating new instance bodies when parameters and interface ports were the same but removed it when I put in a change to allow hierarchical references anywhere in parameter expressions (which is not legal SystemVerilog but I got a bunch of requests for it anyway since apparently the commercial tools mostly allow it). I still plan to go back and re-add the cache but it's somewhat complicated now to figure out when it's safe to cache an instance. |
Yes, currently one per instance. I previously had a cache to avoid creating new instance bodies when parameters and interface ports were the same but removed it when I put in a change to allow hierarchical references anywhere in parameter expressions (which is not legal SystemVerilog but I got a bunch of requests for it anyway since apparently the commercial tools mostly allow it). I still plan to go back and re-add the cache but it's somewhat complicated now to figure out when it's safe to cache an instance.