undriven-port warning is not flagged when the signal is driven in one of the if condition

[lewyitshien]

Is your bug report related to the C++ slang project or the pyslang Python bindings?
C++ slang

Describe the bug
In below case, when COND_A parameter is assigned to 0, output "a" is not assigned to any value. But slang is able to build successfully without any warning.
This behaviour is consistent on slang version 9.1.194+343611be4 (from slang explorer).
It will happen when one of the if condition has output "a" assigned with value.

To Reproduce
Run with -Weverything

module testing #(
    parameter COND_A = 0
) (
    output logic a
);

generate
    if (COND_A) begin : cond_a
        assign a = 0;
    end
    else begin : default_case

    end
endgenerate

endmodule

[MikePopoloski]

This is by design; most people get very annoyed by "unused" lint warnings in shared code that sometimes sets parameters that control generate blocks one way and sometimes another. The idea is that if the warning fires it means the variable / net / port is really never used regardless of param values, which is more likely to indicate a real bug.

[lewyitshien]

I get your point. But I do think the user should do parameter override if the default parameter in the shared code is not controlling the generate block in the way they want. Else this warning is not reflecting the actual undriven port/net/variable based on current parameters set.

[MikePopoloski]

I suppose I could add a flag that controls whether untaken generate blocks are examined or not for the purposes of this warning.

[jcurtiss8086]

Just recently ran into a similar scenario. For the below example, top.a[0] is undriven due to a missing else-clause for the if-generate of module n -- but all other bits of a are driven. I would like to be able to escalate all cases of undriven bits for mult-bit/packed-array/struct ports to an error, but keep any warnings involving non-port signals suppressed.

module m(
    output logic a
);
    always_comb a = 1'b1;
endmodule

module n #(
    bit [3:0] P = 4'hE
) (
    output logic [3:0] a
);

    for (genvar i = 0; i < 4; i++) begin: index
        if (P[i]) begin: valid
            m m1(.a(a[i]));
        end
    end

endmodule

module top;
    logic [3:0] a;
    n n1(.a(a));
endmodule