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better printing
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2 files changed

+152
-8
lines changed

2 files changed

+152
-8
lines changed

‎pipelined/testcases/assembler.py‎

Lines changed: 76 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -215,7 +215,6 @@ def generate_testbench(instructions):
215215
reg reset;
216216
wire end_program;
217217
218-
219218
integer cycle_count = 0;
220219
real execution_time;
221220
real execution_time_ms;
@@ -225,11 +224,13 @@ def generate_testbench(instructions):
225224
initial begin
226225
clk = 0;
227226
reset = 1;
228-
#6 reset = 0;
229227
230-
228+
// Initialize instruction memory first
231229
{instructions}
232-
230+
231+
// promper initialization
232+
#10 reset = 0;
233+
233234
forever #5 clk = ~clk;
234235
end
235236
@@ -250,6 +251,9 @@ def generate_testbench(instructions):
250251
while (!end_program) begin
251252
@(posedge clk);
252253
end
254+
255+
// Allow pipeline to flush completely
256+
repeat (5) @(posedge clk);
253257
254258
// Print register contents
255259
$display("Register file contents:");
@@ -280,6 +284,74 @@ def generate_testbench(instructions):
280284
$finish;
281285
end
282286
287+
always @(posedge clk) begin
288+
if (!reset) begin
289+
cycle_count = cycle_count + 1;
290+
$display("--------------------------------");
291+
$display("Time=%0t, Cycle=%0d", $time, cycle_count);
292+
293+
$display("PIPELINE STATE:");
294+
$display("IF Stage: PC=%h, Instruction=%h", cpu.pc_current, cpu.instruction);
295+
296+
// Decode current instruction in IF stage
297+
if (cpu.instruction != 0) begin
298+
case(cpu.instruction[6:0])
299+
7'b0110011: begin // R-type
300+
case(cpu.instruction[14:12])
301+
3'b000: begin
302+
if (cpu.instruction[31:25] == 7'b0000000)
303+
$display("IF: add x%0d, x%0d, x%0d",
304+
cpu.instruction[11:7], cpu.instruction[19:15], cpu.instruction[24:20]);
305+
else
306+
$display("IF: sub x%0d, x%0d, x%0d",
307+
cpu.instruction[11:7], cpu.instruction[19:15], cpu.instruction[24:20]);
308+
end
309+
3'b111: $display("IF: and x%0d, x%0d, x%0d",
310+
cpu.instruction[11:7], cpu.instruction[19:15], cpu.instruction[24:20]);
311+
3'b110: $display("IF: or x%0d, x%0d, x%0d",
312+
cpu.instruction[11:7], cpu.instruction[19:15], cpu.instruction[24:20]);
313+
endcase
314+
end
315+
7'b0000011: $display("IF: ld x%0d, %0d(x%0d)",
316+
cpu.instruction[11:7], $signed({{52{cpu.instruction[31]}}, cpu.instruction[31:20]}), cpu.instruction[19:15]);
317+
7'b0100011: $display("IF: sd x%0d, %0d(x%0d)",
318+
cpu.instruction[24:20], $signed({{52{cpu.instruction[31]}}, cpu.instruction[31:25], cpu.instruction[11:7]}), cpu.instruction[19:15]);
319+
7'b1100011: $display("IF: beq x%0d, x%0d, %0d",
320+
cpu.instruction[19:15], cpu.instruction[24:20],
321+
$signed({{51{cpu.instruction[31]}}, cpu.instruction[7], cpu.instruction[30:25], cpu.instruction[11:8], 1'b0}));
322+
7'b0010011: $display("IF: addi x%0d, x%0d, %0d",
323+
cpu.instruction[11:7], cpu.instruction[19:15],
324+
$signed({{52{cpu.instruction[31]}}, cpu.instruction[31:20]}));
325+
endcase
326+
end
327+
328+
// Show ID stage activity
329+
$display("ID Stage: rs1=x%0d (%0d), rs2=x%0d (%0d), rd=x%0d",
330+
cpu.rs1, cpu.reg_read_data1, cpu.rs2, cpu.reg_read_data2, cpu.rd);
331+
332+
// Show EX stage activity (removed alu_control as it doesn't exist)
333+
$display("EX Stage: ALU Result=%0h", cpu.alu_result);
334+
335+
// Show MEM stage activity
336+
if (cpu.mem_write)
337+
$display("MEM Stage: Writing %0d to address %0d",
338+
cpu.reg_read_data2, cpu.alu_result);
339+
if (cpu.mem_read)
340+
$display("MEM Stage: Reading from address %0d, value=%0d",
341+
cpu.alu_result, cpu.mem_read_data);
342+
343+
// Show WB stage activity
344+
if (cpu.reg_write && cpu.rd != 0)
345+
$display("WB Stage: Writing %0d to register x%0d",
346+
cpu.reg_write_data, cpu.rd);
347+
348+
// Control signals
349+
$display("Control signals: branch=%b, mem_read=%b, mem_to_reg=%b, mem_write=%b, alu_src=%b, reg_write=%b",
350+
cpu.branch, cpu.mem_read, cpu.mem_to_reg, cpu.mem_write, cpu.alu_src, cpu.reg_write);
351+
352+
end
353+
end
354+
283355
endmodule'''
284356

285357
# Insert the instructions into the template

‎pipelined/verilog/testbench_pipelined.v‎

Lines changed: 76 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,6 @@ module testbench_pipelined();
55
reg reset;
66
wire end_program;
77

8-
98
integer cycle_count = 0;
109
real execution_time;
1110
real execution_time_ms;
@@ -15,16 +14,18 @@ module testbench_pipelined();
1514
initial begin
1615
clk = 0;
1716
reset = 1;
18-
#6 reset = 0;
1917

20-
18+
// Initialize instruction memory first
2119
cpu.imem.memory[0] = 32'b00000000000100000000000010010011;
2220
cpu.imem.memory[1] = 32'b00000000001000000000000100010011;
2321
cpu.imem.memory[2] = 32'b00000000001100000000000110010011;
2422
cpu.imem.memory[3] = 32'b00000000010000000000001000010011;
2523
cpu.imem.memory[4] = 32'b00000000010100000000001010010011;
2624
cpu.imem.memory[5] = 32'b00000000000000000000000000000000;
27-
25+
26+
// promper initialization
27+
#10 reset = 0;
28+
2829
forever #5 clk = ~clk;
2930
end
3031

@@ -45,6 +46,9 @@ module testbench_pipelined();
4546
while (!end_program) begin
4647
@(posedge clk);
4748
end
49+
50+
// Allow pipeline to flush completely
51+
repeat (5) @(posedge clk);
4852

4953
// Print register contents
5054
$display("Register file contents:");
@@ -75,4 +79,72 @@ module testbench_pipelined();
7579
$finish;
7680
end
7781

82+
always @(posedge clk) begin
83+
if (!reset) begin
84+
cycle_count = cycle_count + 1;
85+
$display("--------------------------------");
86+
$display("Time=%0t, Cycle=%0d", $time, cycle_count);
87+
88+
$display("PIPELINE STATE:");
89+
$display("IF Stage: PC=%h, Instruction=%h", cpu.pc_current, cpu.instruction);
90+
91+
// Decode current instruction in IF stage
92+
if (cpu.instruction != 0) begin
93+
case(cpu.instruction[6:0])
94+
7'b0110011: begin // R-type
95+
case(cpu.instruction[14:12])
96+
3'b000: begin
97+
if (cpu.instruction[31:25] == 7'b0000000)
98+
$display("IF: add x%0d, x%0d, x%0d",
99+
cpu.instruction[11:7], cpu.instruction[19:15], cpu.instruction[24:20]);
100+
else
101+
$display("IF: sub x%0d, x%0d, x%0d",
102+
cpu.instruction[11:7], cpu.instruction[19:15], cpu.instruction[24:20]);
103+
end
104+
3'b111: $display("IF: and x%0d, x%0d, x%0d",
105+
cpu.instruction[11:7], cpu.instruction[19:15], cpu.instruction[24:20]);
106+
3'b110: $display("IF: or x%0d, x%0d, x%0d",
107+
cpu.instruction[11:7], cpu.instruction[19:15], cpu.instruction[24:20]);
108+
endcase
109+
end
110+
7'b0000011: $display("IF: ld x%0d, %0d(x%0d)",
111+
cpu.instruction[11:7], $signed({{52{cpu.instruction[31]}}, cpu.instruction[31:20]}), cpu.instruction[19:15]);
112+
7'b0100011: $display("IF: sd x%0d, %0d(x%0d)",
113+
cpu.instruction[24:20], $signed({{52{cpu.instruction[31]}}, cpu.instruction[31:25], cpu.instruction[11:7]}), cpu.instruction[19:15]);
114+
7'b1100011: $display("IF: beq x%0d, x%0d, %0d",
115+
cpu.instruction[19:15], cpu.instruction[24:20],
116+
$signed({{51{cpu.instruction[31]}}, cpu.instruction[7], cpu.instruction[30:25], cpu.instruction[11:8], 1'b0}));
117+
7'b0010011: $display("IF: addi x%0d, x%0d, %0d",
118+
cpu.instruction[11:7], cpu.instruction[19:15],
119+
$signed({{52{cpu.instruction[31]}}, cpu.instruction[31:20]}));
120+
endcase
121+
end
122+
123+
// Show ID stage activity
124+
$display("ID Stage: rs1=x%0d (%0d), rs2=x%0d (%0d), rd=x%0d",
125+
cpu.rs1, cpu.reg_read_data1, cpu.rs2, cpu.reg_read_data2, cpu.rd);
126+
127+
// Show EX stage activity (removed alu_control as it doesn't exist)
128+
$display("EX Stage: ALU Result=%0h", cpu.alu_result);
129+
130+
// Show MEM stage activity
131+
if (cpu.mem_write)
132+
$display("MEM Stage: Writing %0d to address %0d",
133+
cpu.reg_read_data2, cpu.alu_result);
134+
if (cpu.mem_read)
135+
$display("MEM Stage: Reading from address %0d, value=%0d",
136+
cpu.alu_result, cpu.mem_read_data);
137+
138+
// Show WB stage activity
139+
if (cpu.reg_write && cpu.rd != 0)
140+
$display("WB Stage: Writing %0d to register x%0d",
141+
cpu.reg_write_data, cpu.rd);
142+
143+
// Control signals
144+
$display("Control signals: branch=%b, mem_read=%b, mem_to_reg=%b, mem_write=%b, alu_src=%b, reg_write=%b",
145+
cpu.branch, cpu.mem_read, cpu.mem_to_reg, cpu.mem_write, cpu.alu_src, cpu.reg_write);
146+
147+
end
148+
end
149+
78150
endmodule

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