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wig-neshwig-nesh
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instructions begin at instruction address 4
1 parent 574b833 commit a041908

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3 files changed

+19
-141
lines changed

3 files changed

+19
-141
lines changed

‎pipelined/testcases/1.s‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
begin:
2-
addi x0, x0, 1 # does nothing
32
addi x1, x0, 1
43
addi x2, x0, 2
54
addi x3, x0, 3

‎pipelined/testcases/assembler.py‎

Lines changed: 8 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ def main():
4040

4141
# Second pass: generate machine code
4242
current_address = 0
43-
instruction_index = 0
43+
instruction_index = 1
4444
instructions = []
4545

4646
for line in lines:
@@ -221,28 +221,24 @@ def generate_testbench(instructions):
221221
real execution_time_ms;
222222
real execution_time_us;
223223
integer execution_time_p;
224-
224+
225225
initial begin
226226
clk = 0;
227-
forever #5 clk = ~clk;
228-
end
229-
230-
initial begin
231227
reset = 1;
232228
#6 reset = 0;
229+
230+
cpu.imem.memory[0] = 32'b00000000000000000000000000010011;
231+
{instructions}
232+
233+
forever #5 clk = ~clk;
233234
end
234235
235236
cpu_pipelined cpu(
236237
.clk(clk),
237238
.reset(reset),
238239
.end_program(end_program)
239240
);
240-
241-
initial begin
242-
{instructions}
243-
end
244-
245-
241+
246242
integer i;
247243
initial begin
248244
$dumpfile("test_results/cpu_pipelined_test.vcd");
@@ -283,62 +279,6 @@ def generate_testbench(instructions):
283279
284280
$finish;
285281
end
286-
287-
288-
/// signals boi LLMs ki jai ho for formatting
289-
always @(posedge clk) begin
290-
if (!reset) begin
291-
cycle_count = cycle_count + 1;
292-
$display("\\n--------------------------------");
293-
$display("Time=%0t", $time);
294-
$display("PC=%h", cpu.pc_current);
295-
$display("Instruction=%h", cpu.instruction);
296-
297-
case(cpu.instruction[6:0])
298-
7'b0110011: begin
299-
case(cpu.instruction[14:12])
300-
3'b000: $display("Executing: add/sub x%0d, x%0d, x%0d",
301-
cpu.rd, cpu.rs1, cpu.rs2);
302-
3'b111: $display("Executing: and x%0d, x%0d, x%0d",
303-
cpu.rd, cpu.rs1, cpu.rs2);
304-
3'b110: $display("Executing: or x%0d, x%0d, x%0d",
305-
cpu.rd, cpu.rs1, cpu.rs2);
306-
endcase
307-
end
308-
7'b0000011: $display("Executing: ld x%0d, %0d(x%0d)",
309-
cpu.rd, {{52{cpu.instruction[31]}}, cpu.instruction[31:20]}, cpu.rs1);
310-
7'b0100011: $display("Executing: sd x%0d, %0d(x%0d)",
311-
cpu.rs2, {{52{cpu.instruction[31]}}, cpu.instruction[31:20]}, cpu.rs1);
312-
7'b1100011: $display("Executing: beq x%0d, x%0d, %0d",
313-
cpu.rs1, cpu.rs2, $signed({{51{cpu.instruction[31]}}, cpu.instruction[7], cpu.instruction[30:25], cpu.instruction[11:8]}));
314-
7'b0010011: $display("Executing: addi x%0d, x%0d, %0d",
315-
cpu.rd, cpu.rs1, $signed({{53{cpu.instruction[31]}}, cpu.instruction[30:20]}));
316-
endcase
317-
318-
// registers getting used
319-
$display("Register values:");
320-
$display("rs1(x%0d)=%0d", cpu.rs1, cpu.reg_file.registers[cpu.rs1]);
321-
$display("rs2(x%0d)=%0d", cpu.rs2, cpu.reg_file.registers[cpu.rs2]);
322-
if (cpu.reg_write)
323-
$display("Writing to rd(x%0d)=%0d [0x%h]", cpu.rd, cpu.reg_write_data, cpu.reg_write_data);
324-
325-
// control signals
326-
$display("Control signals:");
327-
$display("branch=%0d, mem_read=%0d, mem_to_reg=%0d, mem_write=%0d, alu_src=%0d, reg_write=%0d",
328-
cpu.branch, cpu.mem_read, cpu.mem_to_reg, cpu.mem_write, cpu.alu_src, cpu.reg_write);
329-
330-
// alu result
331-
$display("ALU result=%0d [0x%h]" , cpu.alu_result, cpu.alu_result);
332-
333-
// memory if read/write
334-
if (cpu.mem_write)
335-
$display("Memory write: address=%0d, data=%0d",
336-
cpu.alu_result, cpu.reg_read_data2);
337-
if (cpu.mem_read)
338-
$display("Memory read: address=%0d, data=%0d",
339-
cpu.alu_result, cpu.mem_read_data);
340-
end
341-
end
342282
343283
endmodule'''
344284

‎pipelined/verilog/testbench_pipelined.v‎

Lines changed: 11 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -11,34 +11,29 @@ module testbench_pipelined();
1111
real execution_time_ms;
1212
real execution_time_us;
1313
integer execution_time_p;
14-
14+
1515
initial begin
1616
clk = 0;
17-
forever #5 clk = ~clk;
18-
end
19-
20-
initial begin
2117
reset = 1;
2218
#6 reset = 0;
23-
end
24-
25-
cpu_pipelined cpu(
26-
.clk(clk),
27-
.reset(reset),
28-
.end_program(end_program)
29-
);
30-
31-
initial begin
32-
cpu.imem.memory[0] = 32'b00000000000100000000000000010011;
19+
20+
cpu.imem.memory[0] = 32'b00000000000000000000000000010011;
3321
cpu.imem.memory[1] = 32'b00000000000100000000000010010011;
3422
cpu.imem.memory[2] = 32'b00000000001000000000000100010011;
3523
cpu.imem.memory[3] = 32'b00000000001100000000000110010011;
3624
cpu.imem.memory[4] = 32'b00000000010000000000001000010011;
3725
cpu.imem.memory[5] = 32'b00000000010100000000001010010011;
3826
cpu.imem.memory[6] = 32'b00000000000000000000000000000000;
27+
28+
forever #5 clk = ~clk;
3929
end
40-
4130

31+
cpu_pipelined cpu(
32+
.clk(clk),
33+
.reset(reset),
34+
.end_program(end_program)
35+
);
36+
4237
integer i;
4338
initial begin
4439
$dumpfile("test_results/cpu_pipelined_test.vcd");
@@ -79,61 +74,5 @@ module testbench_pipelined();
7974

8075
$finish;
8176
end
82-
83-
84-
/// signals boi LLMs ki jai ho for formatting
85-
always @(posedge clk) begin
86-
if (!reset) begin
87-
cycle_count = cycle_count + 1;
88-
$display("\n--------------------------------");
89-
$display("Time=%0t", $time);
90-
$display("PC=%h", cpu.pc_current);
91-
$display("Instruction=%h", cpu.instruction);
92-
93-
case(cpu.instruction[6:0])
94-
7'b0110011: begin
95-
case(cpu.instruction[14:12])
96-
3'b000: $display("Executing: add/sub x%0d, x%0d, x%0d",
97-
cpu.rd, cpu.rs1, cpu.rs2);
98-
3'b111: $display("Executing: and x%0d, x%0d, x%0d",
99-
cpu.rd, cpu.rs1, cpu.rs2);
100-
3'b110: $display("Executing: or x%0d, x%0d, x%0d",
101-
cpu.rd, cpu.rs1, cpu.rs2);
102-
endcase
103-
end
104-
7'b0000011: $display("Executing: ld x%0d, %0d(x%0d)",
105-
cpu.rd, {{52{cpu.instruction[31]}}, cpu.instruction[31:20]}, cpu.rs1);
106-
7'b0100011: $display("Executing: sd x%0d, %0d(x%0d)",
107-
cpu.rs2, {{52{cpu.instruction[31]}}, cpu.instruction[31:20]}, cpu.rs1);
108-
7'b1100011: $display("Executing: beq x%0d, x%0d, %0d",
109-
cpu.rs1, cpu.rs2, $signed({{51{cpu.instruction[31]}}, cpu.instruction[7], cpu.instruction[30:25], cpu.instruction[11:8]}));
110-
7'b0010011: $display("Executing: addi x%0d, x%0d, %0d",
111-
cpu.rd, cpu.rs1, $signed({{53{cpu.instruction[31]}}, cpu.instruction[30:20]}));
112-
endcase
113-
114-
// registers getting used
115-
$display("Register values:");
116-
$display("rs1(x%0d)=%0d", cpu.rs1, cpu.reg_file.registers[cpu.rs1]);
117-
$display("rs2(x%0d)=%0d", cpu.rs2, cpu.reg_file.registers[cpu.rs2]);
118-
if (cpu.reg_write)
119-
$display("Writing to rd(x%0d)=%0d [0x%h]", cpu.rd, cpu.reg_write_data, cpu.reg_write_data);
120-
121-
// control signals
122-
$display("Control signals:");
123-
$display("branch=%0d, mem_read=%0d, mem_to_reg=%0d, mem_write=%0d, alu_src=%0d, reg_write=%0d",
124-
cpu.branch, cpu.mem_read, cpu.mem_to_reg, cpu.mem_write, cpu.alu_src, cpu.reg_write);
125-
126-
// alu result
127-
$display("ALU result=%0d [0x%h]" , cpu.alu_result, cpu.alu_result);
128-
129-
// memory if read/write
130-
if (cpu.mem_write)
131-
$display("Memory write: address=%0d, data=%0d",
132-
cpu.alu_result, cpu.reg_read_data2);
133-
if (cpu.mem_read)
134-
$display("Memory read: address=%0d, data=%0d",
135-
cpu.alu_result, cpu.mem_read_data);
136-
end
137-
end
13877

13978
endmodule

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